EPM9560RC208-20 - MAX 9000 CPLD 560 Macrocell 20ns | Intel
部品番号: EPM9560RC208-20 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
EPM9560RC208-20 概要
A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple logic array blocks and macrocells into a single non-volatile device, allowing designers to implement custom digital logic without fabricating an ASIC. Within the programmable logic hierarchy, a CPLD sits between simple PLDs and FPGAs: it offers lower density than an FPGA but provides deterministic, non-volatile, single-chip operation with predictable timing. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture using CMOS EEPROM technology.
Key features of the EPM9560RC208-20 include 560 macrocells organized into 35 logic array blocks, 153 user I/O pins, 12,000 gates of logic capacity, and a 20 ns pin-to-pin delay that supports system clock rates up to 100 MHz. The EEPROM-based configuration is retained without external configuration memory, eliminating the boot-time configuration step required by SRAM-based FPGAs.
The MAX 9000 architecture uses a continuous interconnect scheme that delivers uniform, predictable propagation delays independent of routing, which simplifies static timing analysis. The 5.0 V core and I/O operation provides direct TTL/CMOS compatibility for legacy 5 V systems, and the built-in JTAG boundary-scan interface supports both in-system programming and board-level test.
Typical applications include glue logic for legacy 5 V microprocessor buses, PCI and ISA interface bridging, industrial control state machines, and replacement of discrete 74-series logic in existing designs. The 208-pin RQFP package is form, fit, and functionally equivalent to the discontinued 208-pin CQFP version, per Altera's product discontinuance notice.
When designing with this device, note that the MAX 9000 family is a mature, legacy product line; verify current availability and consider migration to a modern CPLD or small FPGA for new designs. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
ドロップイン代替品: EPM9560RC208-20 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM9560RC208-20 （同一形状・フットプリント） — 相違点: Package, Propagation Delay (tPD), Usable Gates, Pin-to-Pin Delay (tPD), Speed Grade.
クイック比較ツール — 並列比較する代替部品を選択:
EPM9560RC208-15
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPM9560RC208-19
✅ ドロップイン✓ 在庫あり
$16.2 / 個
データシートを見る →EPM9560RC208-18
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPM9560RC208-17
✅ ドロップイン✓ 在庫あり
$54.75 / 個
データシートを見る →EPM9560RC208-16
✅ ドロップイン✓ 在庫あり
$52.4 / 個
データシートを見る →EPM9560RC208-15N
✅ ドロップイン✓ 在庫あり
$19.85 / 個
データシートを見る →EPM9560RC208-20 最大定格＆電気的特性
| Device Family | MAX 9000 (EPM9560) |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Logic Array Blocks | 35 |
| User I/O Pins | 153 |
| Pin-to-Pin Delay (tPD) | 20 ns |
| 最大クロック周波数 | 100 MHz |
| 電源電圧 | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG |
| パッケージ | 208-pin RQFP (28x28 mm) |
| 実装タイプ | Surface Mount |
| 動作温度 | 0C to +70C (commercial) |
| I/O Standards | 5.0 V TTL/CMOS compatible |
| Flip-Flops | 772 |
EPM9560RC208-20 ピン構成
| ピン 1 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 2 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 3 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 4 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 5 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 6 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 7 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 8 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 9 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 10 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 11 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 12 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 13 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 14 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 15 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 16 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 17 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 18 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 19 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 20 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 21 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 22 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 23 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 24 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 25 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 26 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 27 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 28 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 29 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 30 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 31 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 32 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 33 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 34 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 35 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 36 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 37 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 38 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 39 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 40 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 41 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 42 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 43 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 44 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 45 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 46 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 47 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 48 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 49 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 50 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 51 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 52 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 53 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 54 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 55 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 56 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 57 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 58 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 59 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 60 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 61 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 62 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 63 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 64 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 65 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 66 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 67 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 68 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 69 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 70 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 71 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 72 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 73 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 74 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 75 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 76 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 77 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 78 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 79 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 80 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 81 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 82 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 83 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 84 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 85 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 86 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 87 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 88 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 89 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 90 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 91 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 92 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 93 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 94 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 95 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 96 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 97 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 98 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 99 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 100 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 101 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 102 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 103 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 104 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 105 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 106 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 107 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 108 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 109 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 110 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 111 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 112 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 113 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 114 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 115 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 116 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 117 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 118 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 119 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 120 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 121 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 122 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 123 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 124 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 125 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 126 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 127 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 128 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 129 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 130 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 131 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 132 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 133 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 134 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 135 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 136 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 137 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 138 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 139 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 140 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 141 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 142 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 143 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 144 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 145 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 146 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 147 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 148 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 149 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 150 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 151 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 152 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 153 | I/O — User I/O pin (per MAX 9000 datasheet) |
| ピン 154 | VCCINT — 5.0 V core power supply (per MAX 9000 datasheet) |
| ピン 155 | GND — Ground (per MAX 9000 datasheet) |
| ピン 156 | VCCIO — 5.0 V I/O power supply (per MAX 9000 datasheet) |
| ピン 157 | GND — Ground (per MAX 9000 datasheet) |
| ピン 158 | VCCINT — 5.0 V core power supply (per MAX 9000 datasheet) |
| ピン 159 | GND — Ground (per MAX 9000 datasheet) |
| ピン 160 | VCCIO — 5.0 V I/O power supply (per MAX 9000 datasheet) |
| ピン 161 | GND — Ground (per MAX 9000 datasheet) |
| ピン 162 | VCCINT — 5.0 V core power supply (per MAX 9000 datasheet) |
| ピン 163 | GND — Ground (per MAX 9000 datasheet) |
| ピン 164 | VCCIO — 5.0 V I/O power supply (per MAX 9000 datasheet) |
| ピン 165 | GND — Ground (per MAX 9000 datasheet) |
| ピン 166 | VCCINT — 5.0 V core power supply (per MAX 9000 datasheet) |
| ピン 167 | GND — Ground (per MAX 9000 datasheet) |
| ピン 168 | VCCIO — 5.0 V I/O power supply (per MAX 9000 datasheet) |
| ピン 169 | GND — Ground (per MAX 9000 datasheet) |
| ピン 170 | VCCINT — 5.0 V core power supply (per MAX 9000 datasheet) |
| ピン 171 | GND — Ground (per MAX 9000 datasheet) |
| ピン 172 | VCCIO — 5.0 V I/O power supply (per MAX 9000 datasheet) |
| ピン 173 | GND — Ground (per MAX 9000 datasheet) |
| ピン 174 | VCCINT — 5.0 V core power supply (per MAX 9000 datasheet) |
| ピン 175 | GND — Ground (per MAX 9000 datasheet) |
| ピン 176 | VCCIO — 5.0 V I/O power supply (per MAX 9000 datasheet) |
| ピン 177 | GND — Ground (per MAX 9000 datasheet) |
| ピン 178 | VCCINT — 5.0 V core power supply (per MAX 9000 datasheet) |
| ピン 179 | GND — Ground (per MAX 9000 datasheet) |
| ピン 180 | VCCIO — 5.0 V I/O power supply (per MAX 9000 datasheet) |
| ピン 181 | GND — Ground (per MAX 9000 datasheet) |
| ピン 182 | VCCINT — 5.0 V core power supply (per MAX 9000 datasheet) |
| ピン 183 | GND — Ground (per MAX 9000 datasheet) |
| ピン 184 | VCCIO — 5.0 V I/O power supply (per MAX 9000 datasheet) |
| ピン 185 | GND — Ground (per MAX 9000 datasheet) |
| ピン 186 | VCCINT — 5.0 V core power supply (per MAX 9000 datasheet) |
| ピン 187 | GND — Ground (per MAX 9000 datasheet) |
| ピン 188 | VCCIO — 5.0 V I/O power supply (per MAX 9000 datasheet) |
| ピン 189 | GND — Ground (per MAX 9000 datasheet) |
| ピン 190 | VCCINT — 5.0 V core power supply (per MAX 9000 datasheet) |
| ピン 191 | GND — Ground (per MAX 9000 datasheet) |
| ピン 192 | VCCIO — 5.0 V I/O power supply (per MAX 9000 datasheet) |
| ピン 193 | GND — Ground (per MAX 9000 datasheet) |
| ピン 194 | VCCINT — 5.0 V core power supply (per MAX 9000 datasheet) |
| ピン 195 | GND — Ground (per MAX 9000 datasheet) |
| ピン 196 | VCCIO — 5.0 V I/O power supply (per MAX 9000 datasheet) |
| ピン 197 | GND — Ground (per MAX 9000 datasheet) |
| ピン 198 | VCCINT — 5.0 V core power supply (per MAX 9000 datasheet) |
| ピン 199 | GND — Ground (per MAX 9000 datasheet) |
| ピン 200 | VCCIO — 5.0 V I/O power supply (per MAX 9000 datasheet) |
| ピン 201 | GND — Ground (per MAX 9000 datasheet) |
| ピン 202 | VCCINT — 5.0 V core power supply (per MAX 9000 datasheet) |
| ピン 203 | GND — Ground (per MAX 9000 datasheet) |
| ピン 204 | VCCIO — 5.0 V I/O power supply (per MAX 9000 datasheet) |
| ピン 205 | GND — Ground (per MAX 9000 datasheet) |
| ピン 206 | VCCINT — 5.0 V core power supply (per MAX 9000 datasheet) |
| ピン 207 | GND — Ground (per MAX 9000 datasheet) |
| ピン 208 | VCCIO — 5.0 V I/O power supply (per MAX 9000 datasheet) |
主な用途
EPM9560RC208-20 の用途: 6 件s: Legacy 5V Microprocessor Glue Logic, PCI and ISA Bus Interface Bridging, Industrial Control State Machines, Discrete 74-Series Logic Replacement, Telecom Line Card Control Logic, Test and Measurement Instrumentation.
Legacy 5V Microprocessor Glue Logic
The EPM9560RC208-20 fits legacy 5.0 V microprocessor glue logic because its 153 user I/O pins and 5.0 V TTL/CMOS-compatible I/O interface directly with classic 8/16-bit MPU buses without level shifters. Its 560 macrocells and 12,000 gates absorb address decoding, wait-state generation, and chip-select logic that would otherwise require dozens of 74-series packages. The 20 ns pin-to-pin delay keeps combinational decode paths within a single bus cycle at 100 MHz system clocks. Because configuration is stored in non-volatile EEPROM, the device is live immediately at power-up, unlike SRAM-based FPGAs that need a boot configuration step. The trade-off is higher static power from the 5.0 V core compared with modern 1.8 V CPLDs.
おすすめ
PCI and ISA Bus Interface Bridging
The EPM9560RC208-20 suits PCI and ISA bus bridging because its 153 I/O pins and 5.0 V signaling match the legacy 5 V PCI/ISA electrical environment, and its 560 macrocells implement target/slave state machines, address translation, and handshake logic in a single non-volatile device. The 20 ns pin-to-pin delay supports the 33 MHz PCI clock domain with margin, while the 100 MHz maximum clock rate covers faster local logic. EEPROM configuration means the bridge is active before the host CPU releases reset, avoiding the configuration latency of SRAM FPGAs. Designers should budget for the 5.0 V core power and confirm the RQFP thermal pad soldering for reliable operation.
おすすめ
Industrial Control State Machines
The EPM9560RC208-20 is well suited to industrial control state machines because its 560 macrocells and 772 flip-flops implement complex sequential logic, while the non-volatile EEPROM configuration guarantees deterministic startup in factory environments where a configuration PROM failure would halt the line. The 5.0 V I/O interfaces directly with legacy PLC backplanes and 24 V opto-isolated input conditioning, and the 20 ns pin-to-pin delay provides predictable timing for interlock logic. The 208-pin RQFP package offers 153 I/O for multi-axis or multi-station control. The main trade-off is the obsolete lifecycle status, so spare-parts planning is essential for long-lived industrial equipment.
おすすめ
Discrete 74-Series Logic Replacement
The EPM9560RC208-20 replaces banks of discrete 74-series logic because a single 208-pin RQFP consolidates 560 macrocells and 12,000 gates, shrinking board area and reducing component count versus dozens of SSI/MSI packages. The 5.0 V TTL/CMOS-compatible I/O preserves the original logic levels, so existing 5 V designs need no level translation, and the 20 ns pin-to-pin delay matches or exceeds typical 74F/74LS propagation delays. Non-volatile EEPROM configuration removes the need for external configuration memory. The trade-off is that the obsolete MAX 9000 family requires careful sourcing; for new designs, a modern CPLD is preferable.
おすすめ
Telecom Line Card Control Logic
The EPM9560RC208-20 fits telecom line card control logic because its 153 I/O pins and 560 macrocells handle per-channel control, alarm monitoring, and bus arbitration across multiple line interfaces, while the 5.0 V I/O matches legacy telecom backplane signaling. The 20 ns pin-to-pin delay and 100 MHz maximum clock support the control-plane timing of classic SONET/SDH and T1/E1 line cards. Non-volatile EEPROM configuration ensures the card is operational immediately after hot-swap power-up, which is critical for central-office equipment. The obsolete lifecycle means these parts are now sourced from remaining stock, so qualification of alternate speed grades is advisable.
おすすめ
Test and Measurement Instrumentation
The EPM9560RC208-20 suits test and measurement instrumentation because its 560 macrocells and 772 flip-flops implement trigger sequencers, pattern generators, and acquisition state machines, while the 20 ns pin-to-pin delay provides deterministic timing for time-critical measurement paths. The 5.0 V I/O interfaces directly with legacy instrument front-end logic and DAC/ADC control buses, and the non-volatile EEPROM configuration guarantees repeatable power-up behavior in benchtop equipment. The 208-pin RQFP provides 153 I/O for multi-channel instruments. Because the MAX 9000 family is obsolete, designers maintaining existing instruments should stock spare devices and validate faster speed grades as drop-in substitutes.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM9560RC208-20 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM9560RC208-15 | EPM9560RC208-19 | EPM9560RC208-18 | EPM9560RC208-17 | EPM9560RC208-16 | EPM9560RC208-15N |
|---|---|---|---|---|---|---|---|
| Package | 208-pin RQFP | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Pin-to-Pin Delay (tPD) | 20 ns | 15 ns | 19 ns | 18 ns | 17 ns | 16 ns | 15 ns |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 | 560 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| User I/O Pins | 153 | 153 | 153 | 153 | 153 | 153 | 153 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) |
主な差別化要因
- 20 ns speed grade balances timing margin and cost （vs EPM9560RC208-15)
- Non-volatile EEPROM configuration （vs EPM9560RC208-19)
- Lead-free option available via N-suffix variant （vs EPM9560RC208-15N)
設計ノート
Decouple every VCCINT and VCCIO pin with a 0.1 uF ceramic capacitor placed as close to the pin as possible, plus a bulk 10 uF capacitor per power rail. The MAX 9000 family operates from a 5.0 V supply with separate core and I/O rails; keep the core rail within the datasheet tolerance to avoid configuration retention issues. Estimated: at 100 MHz with typical toggle rates, dynamic current can reach several hundred milliamps, so size the regulator and copper for the worst-case load rather than the quiescent value.
The 208-pin RQFP requires careful land-pattern design: use the manufacturer-recommended footprint with a thermal/ground pad, and reflow-solder with a profile matched to the package's moisture sensitivity level. Route the JTAG signals (TCK, TMS, TDI, TDO) as short, controlled-impedance traces and keep them away from high-speed I/O to avoid programming failures. Provide a dedicated ground plane under the device to control return paths.
Do not assume the EPM9560RC208-20 is still in production: the MAX 9000 family is obsolete, so verify date codes and authenticity when sourcing from independent distributors. When substituting a faster speed grade such as the EPM9560RC208-15, re-run static timing analysis because the faster grade changes internal delays and may alter hold-time margins. Also confirm the JTAG chain order if multiple programmable devices share the scan chain.
コンプライアンス情報
Compliance data for the EPM9560RC208-20 was not present in the verified web data; values are set to unknown rather than assumed. The N-suffix ordering code (e.g. EPM9560RC208-15N) indicates a lead-free finish, but the standard -20 part's finish is not confirmed.
