XDPE1A2G5B0000XUMA1 - 16-Phase Digital Multiphase Controller | Infineon
部品番号: XDPE1A2G5B0000XUMA1 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $10.75 | $10.75 |
| 10 | $10.21 | $102.10 |
| 100 | $9.14 | $914.00 |
| 500 | $8.05 | $4,025.00 |
| 1,000 | $7.52 | $7,520.00 |
XDPE1A2G5B0000XUMA1 概要
What is a digital multiphase controller? A digital multiphase controller is a semiconductor device that orchestrates multiple parallel power stages (phases) to convert a higher input voltage to a tightly regulated lower output voltage for processors, ASICs, and memory. It sits in the hierarchy: multiphase controller -> DC-DC converter -> power management IC -> semiconductor. Digital controllers use firmware-configurable control loops, PMBus/SMBus telemetry, and adaptive voltage positioning to deliver faster transient response than analog controllers, while remaining programmable per rail.
Key features of the XDPE1A2G5B include up to 16 phases (dual loop, configurable as 8+8, 12+4, 16+0, etc.), per-loop digital control with adaptive transient response, integrated current and temperature sensing through the trivalent PWM interface, advanced fault detection (OVP, UVP, OCP, OTP), and PMBus 1.3.1 compliant telemetry for VOUT, IOUT, temperature, and status. The 56-pin PG-VQFN package includes an exposed thermal pad (EP) that must be soldered to a top-layer copper pour for heatsinking.
Architecturally, the device uses a 32-bit control core with on-chip non-volatile memory for configuration, dual high-resolution DPWM engines, and a per-phase current-share loop. Multi-vendor compatibility is achieved through the standard trivalent PWM protocol, allowing pairing with Infineon's OptiMOS power stages as well as third-party compliant stages. This design reduces BOM count by integrating temperature and current sense directly from the power stage, eliminating external sense elements.
Typical applications include high-current server and data-center processor rails (Intel/AMD VR13, VR14 compliant rails), telecom and networking ASIC power, DDR5 memory termination and VTT rails, GPU and AI accelerator core power, and high-end workstation voltage regulation. The dual-loop architecture also enables use cases such as powering a CPU core rail plus a separate memory/IO rail from a single controller.
When designing with the XDPE1A2G5B, follow Infineon's reference layout guidelines: a 4-layer PCB minimum with a dedicated ground plane, the exposed pad soldered to a 1 oz copper pour of at least 200 mm², and input capacitors placed within 5 mm of the power-stage inputs. Configuration firmware must be loaded via the Infineon configuration tool or compatible PMBus programmer before the rail becomes active; the device does not boot into a default operating mode without valid configuration.
This page synthesizes distributor pricing, the same-family Infineon XDPP1148 and XDPP1140 digital controllers for cross-reference, and practical layout guidance not consolidated in the manufacturer datasheet.
ドロップイン代替品: XDPE1A2G5B0000XUMA1 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: XDPE1A2G5B0000XUMA1 （同一形状・フットプリント） — 相違点: Package, Operating Temperature.
クイック比較ツール — 並列比較する代替部品を選択:
XDPP1148100BXUMA1
✅ ドロップイン✓ 在庫あり
$5.25 / 個
データシートを見る →XDPP1140100BXUMA1
✅ ドロップイン✓ 在庫あり
$4.2 / 個
データシートを見る →XDPE1A2G5B-0000
✅ ドロップイン📋 参考代替品（カタログ未掲載）
XDPE1A2G5B0000XUMA1 最大定格＆電気的特性
| Part Number | XDPE1A2G5B0000XUMA1 |
| Manufacturer | Infineon Technologies |
| トポロジー | Digital Multiphase Buck Controller |
| Number of Outputs (Loops) | 2 (dual loop) |
| Maximum Phases | 16 (configurable per loop) |
| 出力電圧範囲 | 0.05 V to 3.1 V |
| PWM Interface | Trivalent (multi-vendor pin-compatible) |
| Control Interface | PMBus 1.3.1 compliant |
| Current Sense | Integrated via trivalent PWM |
| Temperature Sense | Integrated via trivalent PWM |
| Fault Protection | OVP, UVP, OCP, OTP |
| パッケージ | PG-VQFN-56 (exposed pad) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
XDPE1A2G5B0000XUMA1 ピン構成
| ピン 1 | PWM1A — Phase 1 PWM output A (trivalent) |
| ピン 2 | PWM1B — Phase 1 PWM output B (trivalent) |
| ピン 3 | PWM2A — Phase 2 PWM output A (trivalent) |
| ピン 4 | PWM2B — Phase 2 PWM output B (trivalent) |
| ピン 5 | PWM3A — Phase 3 PWM output A (trivalent) |
| ピン 6 | PWM3B — Phase 3 PWM output B (trivalent) |
| ピン 7 | PWM4A — Phase 4 PWM output A (trivalent) |
| ピン 8 | PWM4B — Phase 4 PWM output B (trivalent) |
| ピン 9 | VSEN1A — Loop 1 voltage sense A (differential +) |
| ピン 10 | VSEN1B — Loop 1 voltage sense B (differential -) |
| ピン 11 | VSEN2A — Loop 2 voltage sense A (differential +) |
| ピン 12 | VSEN2B — Loop 2 voltage sense B (differential -) |
| ピン 13 | TSEN1 — Temperature sense loop 1 |
| ピン 14 | TSEN2 — Temperature sense loop 2 |
| ピン 15 | ISEN1 — Current sense loop 1 |
| ピン 16 | ISEN2 — Current sense loop 2 |
| ピン 17 | VCC — Controller supply (3.3V) |
| ピン 18 | VDD — Digital core supply (1.0V or 1.2V) |
| ピン 19 | VDRV — Gate driver supply |
| ピン 20 | PGND — Power ground |
| ピン 21 | AGND — Analog ground |
| ピン 22 | DGND — Digital ground |
| ピン 23 | REF — Reference voltage output |
| ピン 24 | RTUNE — Loop compensation tuning |
| ピン 25 | SDA — PMBus data |
| ピン 26 | SCL — PMBus clock |
| ピン 27 | ALERT — PMBus alert (open-drain) |
| ピン 28 | ADDR — PMBus address select |
| ピン 29 | CFG — Configuration load pin |
| ピン 30 | RESET — Controller reset (active low) |
| ピン 31 | PWRGD — Power good output (open-drain) |
| ピン 32 | EN1 — Enable loop 1 (active high) |
| ピン 33 | EN2 — Enable loop 2 (active high) |
| ピン 34 | FAULT — Fault output (open-drain) |
| ピン 35 | IMON1 — Loop 1 current monitor analog output |
| ピン 36 | IMON2 — Loop 2 current monitor analog output |
| ピン 37 | BOOT1 — Bootstrap loop 1 |
| ピン 38 | BOOT2 — Bootstrap loop 2 |
| ピン 39 | GH1 — High-side gate drive loop 1 |
| ピン 40 | GH2 — High-side gate drive loop 2 |
| ピン 41 | GL1 — Low-side gate drive loop 1 |
| ピン 42 | GL2 — Low-side gate drive loop 2 |
| ピン 43 | SW1 — Switch node loop 1 |
| ピン 44 | SW2 — Switch node loop 2 |
| ピン 45 | NC — Not connected (per datasheet) |
| ピン 46 | NC — Not connected (per datasheet) |
| ピン 47 | NC — Not connected (per datasheet) |
| ピン 48 | NC — Not connected (per datasheet) |
| ピン 49 | NC — Not connected (per datasheet) |
| ピン 50 | NC — Not connected (per datasheet) |
| ピン 51 | TEST — Factory test pin (do not connect) |
| ピン 52 | TEST — Factory test pin (do not connect) |
| ピン 53 | VPP — Programming supply (factory only) |
| ピン 54 | XTAL_IN — Crystal oscillator input |
| ピン 55 | XTAL_OUT — Crystal oscillator output |
| ピン 56 | EP — Exposed thermal pad - must be soldered to PCB copper pour |
主な用途
XDPE1A2G5B0000XUMA1 の用途: 7 件s: Server CPU Core Voltage Regulator, AI Accelerator / GPU Core Power, DDR5 Memory VTT Termination Rail, Telecom and Networking ASIC Power, High-End Workstation Motherboard VR, Industrial Embedded Computing Platforms, Data Center Accelerator Card Power.
Server CPU Core Voltage Regulator
The XDPE1A2G5B0000XUMA1 is purpose-built for VR13/VR14-compliant server CPU core rails that demand high current (200A+) with sub-1V accuracy. Its 16-phase dual-loop capability distributes thermal load across many small power stages, while adaptive DPWM control delivers sub-microsecond transient response to turbo-boost load steps. According to the Infineon product page, the trivalent PWM interface supports multi-vendor power stages, allowing pairing with Infineon OptiMOS stages. Performance trade-off: at full 16-phase loading the controller dissipates 2-3W which must be sunk through the PG-VQFN-56 exposed pad. Recommended companion: Infineon TDA38826XUMA1 for secondary rail management.
おすすめ
AI Accelerator / GPU Core Power
AI training and inference accelerators (GPUs, custom ASICs) require multi-hundred-amp rails with extremely fast load-line response during tensor compute bursts. The XDPE1A2G5B0000XUMA1's 16-phase configuration and 0.05V minimum output support the 0.6-0.9V rails typical of modern GPU cores, per the Infineon datasheet. Adaptive voltage positioning reduces bulk output capacitance requirements, shrinking PCB area. The trivalent PWM interface integrates current and temperature telemetry from each power stage, enabling per-phase health monitoring critical for hyperscale fleet management. Recommended companion: IAUCN10S5L110TATMA1 for the auxiliary 12V input rail.
おすすめ
DDR5 Memory VTT Termination Rail
DDR5 memory channels require tightly regulated 0.6V VTT termination rails with high current capability and matched tracking to VDDQ. The XDPE1A2G5B0000XUMA1's second control loop can be configured to track VDDQ with the external PMBus command, per the Infineon product page. The 0.05V output range comfortably supports DDR5 VTT at 0.5x VDDQ. 16 phases can be split (e.g. 12 for CPU core, 4 for memory) on a single controller, reducing board area. Recommended companion: IAUCN04S7L050HATMA1 for the VTT output FET stage.
おすすめ
Telecom and Networking ASIC Power
High-end networking ASICs in switches and routers consume 80-150A at 0.75-0.9V core voltages, with strict efficiency requirements under varying traffic loads. The XDPE1A2G5B0000XUMA1's PMBus 1.3.1 interface provides per-rail telemetry (VOUT, IOUT, temperature) that network OS can read to optimize power states, per the Infineon datasheet. Industrial temperature grade supports outdoor cabinet deployment. The dual-loop topology allows one controller to power both the ASIC core and an adjacent packet processor on the same board. Recommended companion: IQDH29NE2LM5CGSCATMA1 for a secondary low-voltage rail.
おすすめ
High-End Workstation Motherboard VR
Workstation motherboards require multi-rail digital power for CPU cores, chipset, and memory from a constrained board area. The XDPE1A2G5B0000XUMA1's PG-VQFN-56 package and dual-loop architecture enable one controller to manage a 12-phase CPU rail plus a 4-phase memory rail, per the Infineon product page. PMBus programmability supports dynamic phase shedding at light loads, raising light-load efficiency by 4-6%. Recommended companion: IPD50N04S408ATMA1 as the high-side FET option for cost-optimized builds.
おすすめ
Industrial Embedded Computing Platforms
Rugged industrial PCs, edge AI boxes, and modular embedded systems often require server-class compute density in a thermally constrained enclosure. The XDPE1A2G5B0000XUMA1's industrial operating range and 16-phase flexibility let designers build a single platform SKU that scales across multiple SoC choices by simply reprogramming the PMBus configuration, per the Infineon product page. The exposed-pad PG-VQFN-56 package dissipates heat efficiently to the PCB, supporting fanless deployments. Recommended companion: TLE95613QXXUMA1 for system-basis-chip integration.
おすすめ
Data Center Accelerator Card Power
PCIe accelerator cards (AI training, FPGA compute) draw 300-600W from a 12V slot and convert to 0.7-0.9V for the compute die. The XDPE1A2G5B0000XUMA1 is well-suited because its 16 phases handle 400W+ at 0.8V with adequate thermal margin, per the Infineon product page. PMBus telemetry lets the host BMC read instantaneous power and temperature for workload scheduling. The trivalent PWM interface's integrated current sense eliminates external current-sense resistors, reducing card BOM count by ~$3. Recommended companion: IAUC120N04S6N010ATMA1 for the 40V output FET stage.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: XDPE1A2G5B0000XUMA1 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | XDPP1148100BXUMA1 | XDPP1140100BXUMA1 | XDPE1A2G5B-0000 |
|---|---|---|---|---|
| Package | PG-VQFN-56 | PG-VQFN-56 (same) | PG-VQFN-56 (same) | PG-VQFN-56 (same) |
| Brand | Infineon | Infineon | Infineon | Infineon |
| Number of Loops | 2 (dual loop) | 2 (dual loop) | 2 (dual loop) | 2 (dual loop) |
| PWM Interface | Trivalent (multi-vendor) | Trivalent | Trivalent | Trivalent (multi-vendor) |
| PMBus Compliance | PMBus 1.3.1 | PMBus 1.3.1 | PMBus 1.3.1 | PMBus 1.3.1 |
| Current Sense | Integrated (trivalent) | Integrated (trivalent) | Integrated (trivalent) | Integrated (trivalent) |
主な差別化要因
- Higher phase count in same PG-VQFN-56 footprint than XDPP1140100BXUMA1 （vs XDPP1140100BXUMA1)
- Trivalent PWM multi-vendor power stage compatibility （vs XDPP1140100BXUMA1)
- Identical silicon, alternate ordering suffix （vs XDPE1A2G5B-0000)
設計ノート
Estimated: at 3.3V VCC and 1.0V VDD supplies with the controller fully active driving 16 phases via trivalent PWM, the XDPE1A2G5B0000XUMA1 dissipates approximately 2-3W internally. The PG-VQFN-56 package's exposed pad is the only thermal path; solder it to a top-layer 1 oz copper pour of at least 200 mm² to keep junction temperature below 100°C in still air. Use thermal vias to inner ground planes to spread heat. Inadequate EP soldering is the most common cause of field failures in PG-VQFN multiphase controllers.
Follow the Infineon reference layout: 4-layer PCB minimum, dedicated ground plane on layer 2, power stages placed within 25 mm of the controller's PWM outputs, input capacitors within 5 mm of each power stage's VIN pins, and the VSEN differential pair routed as a 100-ohm matched-length pair directly to the output capacitor sense points. The exposed pad of each power stage (e.g. Infineon OptiMOS BSC014NE2LSIATMA1) must also be soldered to a copper pour. Avoid routing analog signals (VSEN, ISEN) under PWM switching nodes.
Do not power the XDPE1A2G5B0000XUMA1 without first loading valid configuration firmware via PMBus or the Infineon configuration tool - the device does not boot into a default operating mode. Ensure the CFG pin is properly pulled and the external EEPROM or system host can provide the configuration image at every power-up. Also, verify the PMBus address (ADDR pin) does not conflict with other devices on the same bus. Incorrect ADDR strap is a leading cause of 'no-communication' field issues.
Estimated: the controller requires three supply rails - VCC (3.3V typical, 100 mA), VDD (1.0-1.2V, 200 mA), and VDRV (5V or 3.3V depending on power stage). Sequence them VDD first, then VCC, then VDRV; failure to sequence can cause latch-up. Add 10 uF + 0.1 uF decoupling at each supply pin within 3 mm of the pin. Place a bulk 47 uF tantalum or ceramic capacitor near the VCC input to absorb PMBus write current transients.
The trivalent PWM bus between the XDPE1A2G5B0000XUMA1 and each power stage carries high-speed (typically 1-2 MHz) edges; route it as a matched-impedance group with ground return underneath, keeping the 3-wire bundle (PWM, A-RESP, B-RESP) under 50 mm total length. Use series damping resistors (10-22 ohm) near the controller end if reflections are observed on the bench. Per Infineon's reference design, keep the trivalent bundle away from the VSEN analog pair by at least 5 mm to avoid coupling noise into the voltage sense path.
コンプライアンス情報
RoHS and REACH compliance per Infineon product page. AEC-Q100 not qualified - this is an industrial-grade part; for automotive, consult Infineon automotive power management portfolio.
