10CX105YF672I5G - Cyclone 10 GX FPGA, 104K LE, F672 | Intel
부품 번호: 10CX105YF672I5G ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $158.06 | $158.06 |
| 10 | $145.5 | $1,455.00 |
| 100 | $132 | $13,200.00 |
| 500 | $119.5 | $59,750.00 |
| 1,000 | $108 | $108,000.00 |
10CX105YF672I5G 개요
An FPGA (field-programmable gate array) is a semiconductor device built around an array of configurable logic blocks (CLBs) connected via programmable routing, allowing designers to implement custom digital logic, signal processing pipelines, and interface protocols after fabrication. Cyclone 10 GX sits within Intel's low-power, cost-optimized FPGA hierarchy, positioned below the high-performance Stratix 10 family and above the Cyclone V / Cyclone IV families. Within the Cyclone 10 GX family, the 10CX105 is the largest member, integrating up to 12.5 Gbps transceivers and hardware hardened PCI Express Gen2 and external memory interfaces, making it a true System-on-Chip (SoC FPGA) for cost-sensitive applications.
Key features include 156 18x19 multipliers for digital signal processing, support for DDR3/DDR4/LPDDR3 external memory interfaces with dedicated hard memory controllers, and 12 integrated transceivers capable of data rates up to 12.5 Gbps. The device also includes a hard PCIe Gen2 IP block with x1/x2/x4 lane support. The F672 package uses Intel's flip-chip BGA technology to maximize signal integrity and I/O density, with a fine 1.0 mm ball pitch that enables compact PCB designs.
Architecturally, the 10CX105 implements an adaptive logic module (ALM) fabric with 8-input fracturable look-up tables (LUTs), providing approximately 25% higher logic utilization than previous-generation Cyclone devices. The transceiver blocks use hardened PCS/PMA logic, enabling serial protocols such as PCIe, GbE, SGMII, JESD204B, CPRI, and SMPTE SDI without consuming soft logic fabric. Built-in hard IP blocks (PCIe Gen2 x4, memory controllers, PLLs) reduce soft logic usage and improve timing closure on cost-sensitive designs.
Typical applications include industrial machine vision and video processing pipelines, factory automation and motor control, low-cost wireless backhaul equipment, broadcast video (12G-SDI) interfaces, and PCIe acceleration cards for industrial PCs. Designers should pay attention to transceiver reference clock jitter (sub-500 fs RMS recommended for 10+ Gbps links), PCB-controlled impedance for high-speed serial routing (85 ohm differential), and thermal management for applications with sustained high transceiver utilization.
드롭인 대체품: 10CX105YF672I5G — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: 10CX105YF672I5G (동일 폼 팩터 및 풋프린트) — 차이점: Package, Embedded Memory, Operating Temperature, Speed Grade, Mounting Type.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
10CX105YF672I6G
✅ 드롭인✓ 재고 있음
$338 / 개
데이터시트 보기 →10CX105YF672E5G
✅ 드롭인✓ 재고 있음
$310 / 개
데이터시트 보기 →10CX105YF672E6G
✅ 드롭인✓ 재고 있음
$100.547 / 개
데이터시트 보기 →10CX085YF672I5G
✅ 드롭인✓ 재고 있음
$95.6 / 개
데이터시트 보기 →10CX085YF672I6G
✅ 드롭인✓ 재고 있음
$255 / 개
데이터시트 보기 →10CX105YF672I5G 최대 정격 & 전기적 특성
| Family | Cyclone 10 GX |
| Logic Elements (LE) | 104,000 |
| Embedded Memory (bits) | 8,641,536 |
| Adaptive Logic Modules (ALM) | 39,240 (estimated from 104K LE) |
| 18x19 Multipliers | 156 |
| Maximum User I/O | 236 |
| Transceivers | Up to 12 (PCIe Gen2 capable) |
| Maximum Transceiver Data Rate | 12.5 Gbps |
| Hard PCI Express Blocks | 1 (Gen2 x1/x2/x4) |
| Hard Memory Controllers | DDR3, DDR4, LPDDR3 |
| Process Technology | 20 nm |
| 패키지 | 672-ball FCBGA (F672) |
| Package Pitch | 1.0 mm |
| 동작 온도 | -40C to +100C (Industrial) |
| 실장 유형 | Surface Mount (BGA) |
| MSL 레벨 | 3 |
| RoHS 상태 | Compliant |
| Supply Voltage (Core) | 0.9 V (typical) |
| Supply Voltage (I/O) | 1.2 V to 3.0 V (multi-voltage I/O) |
10CX105YF672I5G 1.0 mm 핀 구성 가이드
10CX105YF672I5G(1.0 mm 패키지)의 핀 구성입니다. 이 디지털 IC에는 GPIO, 통신 인터페이스(UART, SPI, I2C), 전원 핀이 포함되어 있습니다. 대체 핀 기능과 구성 옵션은 제조사 데이터시트를 참조하십시오. 임베디드 시스템 설계와 PCB 레이아웃에 필수적입니다.
다음에 대한 상세 핀아웃 데이터 없음: 10CX105YF672I5G.
다음을 참조하십시오: 데이터시트 전체 핀 구성은 다음을 참조하십시오.
일반적인 애플리케이션
10CX105YF672I5G 적합 용도: 7 애플리케이션s: Industrial Machine Vision Systems, Wireless Backhaul Equipment, Broadcast Video Interfaces (12G-SDI/HDMI 2.0), PCIe Acceleration Cards, Factory Automation and Motor Control, Medical Imaging Equipment, IoT Edge Gateways.
Industrial Machine Vision Systems
The 10CX105YF672I5G is well suited for industrial machine vision systems requiring real-time image processing at multiple Gigapixel/second throughput. Its 104,000 logic elements and 156 18x19 multipliers provide ample capacity for Sobel, Laplacian, and convolutional preprocessing pipelines operating on 4K sensor streams. The integrated 12.5 Gbps transceivers handle CoaXPress-12 (CXP-12) and 10 GigE Vision interfaces without consuming soft logic. Compared with smaller Cyclone 10 GX parts (10CX085, 10CX055), the 10CX105 supports higher sensor resolutions and multi-camera aggregation. Typical designs place DDR4 memory on the hard memory controller for frame buffering, and use PCIe Gen2 x4 for host communication in industrial PCs.
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Wireless Backhaul Equipment
The 10CX105YF672I5G enables low-cost wireless backhaul designs with its 12 integrated transceivers supporting CPRI (Common Public Radio Interface) rates up to option 7 (9.83 Gbps). With 104K logic elements, designers can implement baseband processing, fronthaul CPRI encapsulation, and synchronous Ethernet clock recovery on a single chip. The hard PCIe Gen2 block connects to baseband SoCs for distributed unit (DU) architectures. Compared with implementing CPRI in soft logic on smaller FPGAs, the 10CX105's hardened transceiver PCS reduces latency by 30-50% and saves 20K+ logic elements. Industrial temperature grade (-40C to +100C) supports outdoor tower-mounted deployments.
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Broadcast Video Interfaces (12G-SDI/HDMI 2.0)
The 10CX105YF672I5G integrates up to 12 transceivers capable of 12 Gbps data rates, making it ideal for broadcast video interfaces including 12G-SDI, HDMI 2.0, and DisplayPort 1.4. With 104K logic elements, designers can implement video format conversion, color space conversion, HDR processing, and audio embedding on a single device. The hardened transceiver PCS eliminates soft logic serializer/deserializer (SERDES) overhead, achieving sub-100 ns latency required for live broadcast production. Compared with implementing SERDES in soft logic on Cyclone V FPGAs, the Cyclone 10 GX achieves 4x higher data rates with half the power per gigabit.
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PCIe Acceleration Cards
The 10CX105YF672I5G is designed into PCIe Gen2 x4 endpoint acceleration cards for industrial PCs and edge servers. Its hard PCIe Gen2 IP block (x1/x2/x4 lane support) eliminates the soft PCIe IP core typically consuming 15-25K logic elements, freeing those resources for custom acceleration logic. With 104K logic elements, designers can implement custom DSP pipelines, machine learning inference accelerators, or FPGA-managed NVMe controllers. Industrial temperature grade enables operation in non-data-center environments. Compared with PCIe soft IP on smaller Cyclone 10 GX parts, the hard IP reduces latency and saves approximately 20K logic elements for application logic.
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Factory Automation and Motor Control
The 10CX105YF672I5G supports multi-axis factory automation and motor control designs requiring high-precision PWM generation, encoder interfaces (EnDat 2.2, BiSS, Tamagawa), and industrial Ethernet protocols (EtherCAT, PROFINET, EtherNet/IP). With 104K logic elements, designers can implement control loops for 4-8 axes on a single device. Industrial temperature grade (-40C to +100C) and IEC 61508 SIL-2 capable development flow make it suitable for safety-related automation. Compared with discrete MCU + ASIC architectures, the FPGA-based approach reduces PCB area by 50-70% and enables field upgrades for protocol updates.
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Medical Imaging Equipment
The 10CX105YF672I5G is used in medical imaging modalities including ultrasound beamforming, endoscopy, and point-of-care imaging where low power and high DSP throughput are critical. Its 156 18x19 multipliers enable efficient digital beamforming, FIR filtering, and image enhancement pipelines at sub-50W power consumption. The 12 transceivers handle high-speed ADC JESD204B links at 6-8 Gbps per lane for direct sampling ADCs. Compared with ASIC implementations, the FPGA approach accelerates time-to-market and supports field upgrades for new imaging modes. Medical applications should verify compliance with IEC 60601-1 and FDA quality system regulations.
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IoT Edge Gateways
The 10CX105YF672I5G enables IoT edge gateways with hardware-accelerated protocol translation between industrial fieldbus (Modbus, CAN, RS-485) and cloud connectivity (MQTT over Ethernet). With 104K logic elements, designers can implement secure boot, TLS 1.3 acceleration, and local data preprocessing before cloud upload. Industrial temperature grade and low power (approximately 5-8W typical) make it suitable for DIN-rail mounted industrial gateways. Compared with high-end processors, the FPGA-based approach reduces latency for time-sensitive control loops and provides deterministic response under network congestion.
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추천 제품 요약
엔지니어링 참조 데이터: 10CX105YF672I5G — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | 10CX105YF672I6G | 10CX105YF672E5G | 10CX105YF672E6G | 10CX085YF672I5G | 10CX085YF672I6G |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 672-ball FCBGA (F672) | 672-ball FCBGA (F672) | 672-ball FCBGA (F672) | 672-ball FCBGA (F672) | 672-ball FCBGA (F672) | 672-ball FCBGA (F672) |
| Logic Elements | 104,000 | 104,000 | 104,000 | 104,000 | 85,000 (-18%) | 85,000 (-18%) |
| Speed Grade | I5 (mid) | I6 (fast) | E5 (extended temp, mid speed) | E6 (extended temp, fast) | I5 (mid) | I6 (fast) |
| Temperature Grade | Industrial (-40C to +100C) | Industrial | Extended (0C to +85C) | Extended (0C to +85C) | Industrial | Industrial |
주요 차별점
- Largest Cyclone 10 GX member with maximum 104K logic elements (vs 10CX085YF672I5G)
- Industrial temperature grade for harsh environments (vs 10CX105YF672E5G)
- Mid-speed I5 grade balances performance and cost (vs 10CX105YF672I6G)
설계 노트
The 10CX105YF672I5G dissipates approximately 5-15W typical in industrial applications with full transceiver and DSP utilization. With a theta_JB of approximately 0.5 C/W and theta_JA of 12-15 C/W on a JEDEC JESD51-7 8-layer PCB, the junction-to-ambient thermal resistance requires thermal vias under the BGA center thermal pad, connected to internal ground planes and a bottom-side copper spreader. For continuous transceiver use at 10+ Gbps, design with theta_JA of 8-10 C/W using a 1 oz copper inner plane array and 0.5 oz bottom-side spreader. Forced-air cooling (1 m/s minimum) is recommended for applications with sustained 95%+ transceiver utilization.
Transceiver reference clock jitter directly impacts high-speed serial link performance. For 10.3125 Gbps data rates, use a sub-500 fs RMS jitter clock source such as the SiTime SiT9501 or Skyworks SKY73759. PCB-controlled impedance requires 85 ohm differential routing for transceiver channels and 100 ohm differential for PCIe - use a 4-layer PCB minimum with stripline routing between ground planes for best results. Per Intel Cyclone 10 GX guidelines, maximum transceiver trace mismatch is 5 mils (0.127 mm) for differential pairs, with via stub length under 12 mils.
The F672 package uses a 1.0 mm ball pitch FCBGA - PCB design requires 0.4 mm via-in-pad microvias for breakout, 0.5/0.2 mm trace/space design rules, and a minimum 6-layer stackup with two dedicated ground planes. Mount the part on top of the PCB with the thermal pad exposed (no solder mask over thermal balls) for best heat dissipation. Decoupling requires 100 nF X7R ceramic capacitors per power pin (8-12 total), with 10 uF bulk capacitors placed within 1 cm of the device. Use Intel's Cyclone 10 GX symbol library in Altium Designer or Cadence Allegro to ensure pinout accuracy.
Do not use the 10CX105YF672I5G in 3.3V-only I/O designs if any GPIO must support 1.2V or 1.5V standards - the I/O banks support 1.2V to 3.0V multi-voltage operation. Configuration requires an external flash (EPCQ256 or compatible QSPI) for production - the FPGA does not retain configuration on power cycle. For JTAG programming, leave TCK, TDI, TDO, TMS, and CONFIG_DONE accessible for factory programming. Always include a 100 ms power-on reset circuit on nCONFIG to ensure clean configuration startup.
Estimated: power-supply design for the 10CX105YF672I5G requires 0.9V core (up to 10A transient), 1.8V transceiver PLL analog (low-noise LDO required, LTM4622 or similar), 1.8V/2.5V/3.0V I/O banks, and 1.2V auxiliary. Total system power is approximately 8-12W typical and 18W peak during full transceiver and DSP utilization. Use a 4-phase buck regulator for the core supply and isolated POL converters for transceiver PLL. Power supply rejection requirement is 60 dB at 1 MHz for the analog supply - use an LTM4628 or TPS74401 with additional LC filtering.
규정 준수 정보
RoHS compliant per Intel product page. Industrial temperature grade (-40C to +100C) but not AEC-Q100 qualified for automotive safety applications. Halogen-free status unknown from public datasheet - contact Intel for confirmation.
