EP20K400EFC672-2 - 400K Gates APEX 20KE FPGA | Intel / Altera
부품 번호: EP20K400EFC672-2 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $145 | $145.00 |
| 10 | $132 | $1,320.00 |
| 100 | $118.5 | $11,850.00 |
| 500 | $105 | $52,500.00 |
| 1,000 | $92.75 | $92,750.00 |
EP20K400EFC672-2 개요
An FPGA (Field Programmable Gate Array) is a type of programmable logic device (PLD) that allows engineers to implement custom digital circuits by configuring an array of configurable logic blocks (CLBs), interconnect, and I/O cells after manufacturing. FPGAs sit hierarchically between simple programmable logic (CPLDs) and fixed-function ASICs, offering higher logic density than CPLDs but lower per-unit cost than full ASICs at low volumes. APEX 20KE devices extend the original APEX 20K family by adding MultiCore interconnect and embedded memory, occupying the high-density tier within Altera's programmable logic portfolio at the time of release.
Key features of the EP20K400EFC672-2 include 212,992 bits of embedded RAM, 488 maximum user I/Os, a 1.8V core supply with 2.5V tolerant I/O support, and a commercial operating temperature range of 0C to 85C. The FC-FBGA-672 package provides a 1.0 mm ball pitch, supporting high-pin-count designs with controlled impedance signal integrity. The device supports in-system programmability via JTAG and configuration via serial or parallel PROM interfaces, and was widely used in designs that required rapid prototyping before ASIC conversion.
The APEX 20KE architecture integrates four types of logic structures: LUTs for register-intensive datapaths, product-term logic for control state machines, ESBs that can act as dual-port RAM, ROM, or CAM, and a high-bandwidth MultiCore interconnect that ties the structures together. This heterogeneous fabric allowed designers to place LUT-based and product-term logic in the same device without sacrificing utilization, an advantage over pure LUT-based FPGAs of that generation.
Typical applications for the EP20K400EFC672-2 include telecommunications line cards, baseband processing in early 3G infrastructure, networking switches and routers, custom DSP pipelines, and PCI bus interface bridging. The high I/O count and embedded memory made it well-suited for packet processing engines and protocol conversion functions where multiple parallel interfaces had to be absorbed on a single device.
When designing with this device, engineers should note that APEX 20KE parts have reached end-of-life status from Intel/Altera, and new designs should target Cyclone, Arria, or Stratix families. Existing designs should consider lifetime-buy planning and verify that the Quartus II design software version (13.0 SP1 or earlier for APEX support) is still available in the engineer's design flow.
This page synthesizes distributor pricing, lifecycle status, drop-in alternatives from the same APEX 20KE family, and practical design notes that complement the official APEX 20KE datasheet from Altera. All specifications are cross-referenced against DigiKey, Mouser, and Octopart listings as of 2026-09-08.
드롭인 대체품: EP20K400EFC672-2 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EP20K400EFC672-2 (동일 폼 팩터 및 풋프린트) — 차이점: Operating Temperature, Process Technology, Package, Family, Series.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EP20K400EFC672-2N
✅ 드롭인✓ 재고 있음
$171 / 개
데이터시트 보기 →EP20K400EFC672-2X
✅ 드롭인✓ 재고 있음
$118.9 / 개
데이터시트 보기 →EP20K400EFC672-1XN
✅ 드롭인✓ 재고 있음
$215 / 개
데이터시트 보기 →EP20K400EFC672-1N
✅ 드롭인✓ 재고 있음
$175 / 개
데이터시트 보기 →EP20K400EFC672-1
✅ 드롭인✓ 재고 있음
$110 / 개
데이터시트 보기 →EP20K400EFC672-2 최대 정격 & 전기적 특성
| Family | APEX 20KE |
| Logic Elements / Cells | 16640 |
| Total RAM Bits | 212992 |
| Number of I/O | 488 |
| Number of Logic Gates | 400000 |
| Core Voltage | 1.8 V |
| Propagation Delay | 2.5 ns |
| 동작 온도 | 0 C to 85 C |
| Package Type | FC-FBGA |
| Package Pin Count | 672 |
| 실장 유형 | Surface Mount |
| Logic Family | CMOS |
| Process Technology | 0.22 um |
EP20K400EFC672-2 핀 구성
| 핀 A1 | I/O — General-purpose user I/O ball |
| 핀 A2 | I/O — General-purpose user I/O ball |
| 핀 A3 | VCCINT — Core supply voltage (1.8V) |
| 핀 A4 | I/O — General-purpose user I/O ball |
| 핀 B1 | I/O — General-purpose user I/O ball |
| 핀 B2 | GND — Ground reference |
| 핀 B3 | I/O — General-purpose user I/O ball |
| 핀 B4 | VCCIO — I/O bank supply voltage |
| 핀 C1 | I/O — General-purpose user I/O ball |
| 핀 C2 | I/O — General-purpose user I/O ball |
| 핀 C3 | TCK — JTAG test clock input |
| 핀 C4 | TMS — JTAG test mode select |
| 핀 D1 | TDI — JTAG test data input |
| 핀 D2 | TDO — JTAG test data output |
| 핀 D3 | nCONFIG — Configuration control (active low) |
| 핀 D4 | nSTATUS — Configuration status (active low) |
| 핀 E1 | CONF_DONE — Configuration complete indicator |
| 핀 E2 | DCLK — Configuration clock |
| 핀 E3 | DATA0 — Configuration data input |
| 핀 E4 | I/O — General-purpose user I/O ball |
일반적인 애플리케이션
EP20K400EFC672-2 적합 용도: 6 애플리케이션s: Telecom Line Card Processing, Custom DSP Pipeline Implementation, Networking Switch and Router Bridging, PCI Bus Interface Bridging, ASIC Prototyping and Logic Emulation, Industrial Control and Test Equipment.
Telecom Line Card Processing
The EP20K400EFC672-2 is well-matched to telecom line card processing because its 400K gates and 212,992 bits of embedded RAM can absorb protocol-terminating state machines, packet buffers, and serializer/deserializer glue logic in a single device. Its 488 user I/Os easily support multi-standard backplane interfaces including H.110, TDM, and POS/PHY connections. Operating at 1.8V core with 2.5 ns propagation delay, the device meets the latency budgets of voice and early 3G baseband processing. Place the FPGA between physical-layer transceivers and the host network processor, using ESBs in dual-port RAM mode to implement FIFO buffers across clock domains.
추천
Custom DSP Pipeline Implementation
The EP20K400EFC672-2's 16640 logic elements and MultiCore architecture allow implementation of multi-stage DSP datapaths including FIR filters, FFT butterflies, and custom correlators without external DSP chips. The 212,992 embedded RAM bits are sufficient for coefficient storage and ping-pong sample buffers at sample rates up to the device's 2.5 ns propagation-delay budget. Use LUT-based logic for arithmetic and ESBs as ROM lookups for sine/cosine tables or windowing coefficients. This application fits instrumentation, sonar, and early-3G channel cards where a fixed-function DSP is too inflexible.
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Networking Switch and Router Bridging
The EP20K400EFC672-2's 488 user I/Os and 400K gate capacity make it well suited for bridging between multiple network PHYs, switch fabrics, and host processors in mid-range networking equipment. The 2.5 ns propagation delay supports line-rate processing for Fast Ethernet and Gigabit Ethernet MAC functions, while ESBs provide the buffering required for store-and-forward and cut-through switching. Use the APEX 20KE's LUT fabric for header parsing and product-term logic for TCAM-like lookup decision trees. The 672-ball FC-FBGA package also delivers the controlled-impedance signal integrity needed for MII/RGMII/SGMII interfaces.
추천
PCI Bus Interface Bridging
The EP20K400EFC672-2's 488 I/O count easily accommodates 64-bit PCI or PCI-X bus interfaces plus local-bus glue, target-state machines, and DMA controllers in a single device. The 1.8V core with 2.5V/3.3V-tolerant I/O banks allow direct connection to legacy PCI signals without external level shifters. The 16,640 logic elements are sufficient for scatter-gather DMA engines, master/target arbitration, and message-signaled interrupt controllers. This makes the part well suited for legacy industrial controllers, embedded SBCs, and test equipment that must remain PCI-compatible.
추천
ASIC Prototyping and Logic Emulation
The EP20K400EFC672-2 was a popular choice for ASIC prototyping because its 400K gates and 488 I/Os allowed partitioning large ASIC designs into a small number of APEX 20KE devices for bring-up and validation. The 1.8V core and 2.5 ns propagation delay deliver reasonable timing correlation with 0.18um and 0.22um ASIC processes of the same era. The 212 Kbit embedded RAM supports scratchpad memory and bus-functional model state, while the JTAG port enables in-system debug. Place multiple EP20K400EFC672-2 devices on a multi-FPGA emulator board to validate ASIC RTL before tape-out.
추천
Industrial Control and Test Equipment
The EP20K400EFC672-2's combination of 488 user I/Os, embedded RAM, and 0C-85C commercial temperature range makes it suitable for industrial test-and-measurement chassis where many parallel signal channels must be acquired, processed, and forwarded. The APEX 20KE's product-term logic accelerates parallel-bit decision trees used in boundary-scan, JTAG-chain control, and ATE pin-electronics coordination. Operating from a 1.8V core with multi-voltage I/O support, the device can interface to legacy 5V instrumentation as well as 3.3V mixed-signal front ends. This application remains common in long-lifecycle production testers that are still in field service.
추천
추천 제품 요약
엔지니어링 참조 데이터: EP20K400EFC672-2 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EP20K400EFC672-2N | EP20K400EFC672-2X | EP20K400EFC672-1XN |
|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | FC-FBGA-672 | FC-FBGA-672 - same | FC-FBGA-672 - same | FC-FBGA-672 - same |
| Logic Elements | 16640 | 16640 | 16640 | 16640 |
| Total Gates | 400000 | 400000 | 400000 | 400000 |
| Embedded RAM Bits | 212992 | 212992 | 212992 | 212992 |
| User I/Os | 488 | 488 | 488 | 488 |
| Speed Grade | -2 | -2 | -2 | -1 (slower) |
| Operating Temperature | 0C to 85C (commercial) | 0C to 85C | Extended grade | Industrial grade |
주요 차별점
- Highest user I/O count in the APEX 20KE 400K-gate tier (vs EP20K300EFC672-2)
- Drop-in lead-free variant available without redesign (vs EP20K400EFC672-2N)
- Same-family industrial temperature alternative (vs EP20K400EFC672-1XN)
설계 노트
Estimated: Because the APEX 20KE family is obsolete, the only supported design software is Quartus II version 13.0 SP1 or earlier. Newer Quartus versions do not include APEX device support. Maintain a licensed copy of Quartus II 13.0 SP1 and a parallel Altera programming hardware chain (USB-Blaster or ByteBlaster) for ongoing bitstream generation.
Estimated: At maximum utilization (approximately 80% of 16640 logic elements switching at 50 MHz in the 672-ball FC-FBGA package), the EP20K400EFC672-2 dissipates roughly 1.5-2 W. The 1.0 mm ball pitch FC-FBGA requires a minimum 6-layer PCB stack-up with continuous ground and 1.8V power planes directly beneath the device to spread heat and provide low-impedance power delivery.
Estimated: Each VCCINT and VCCIO ball must be decoupled with a 0.1uF ceramic capacitor placed within 2 mm of the package ball, plus a 10uF bulk capacitor per power region. Use multiple GND balls stitched with vias to the inner ground plane to control return-current paths for the 488 high-speed I/Os at their switching edges.
규정 준수 정보
Compliance status not stated in verified web data; the -2N suffix variant indicates a lead-free option is available in the same package. Industrial/automotive certifications are not applicable for this obsolete commercial-grade FPGA.
