Intel

EP3SL200H780I4L - 200K Logic Elements Stratix III L FPGA | Intel

부품 번호: EP3SL200H780I4L ✗ 단종

재고 있음 영업일 기준 1~3일 내 발송

0.86 V to 1.15 V Vdss 780-pin FC-HFBGA (Flip-Chip) Package I4 (Industrial) Speed 10,901,504 Memory

시작가 $1395 USD / 개

MOQ: 1 |

가격 업데이트: 2026-09-09

볼륨 가격

수량	단가	합계
1	$1850	$1,850.00
10	$1725	$17,250.00
100	$1610	$161,000.00
500	$1480	$740,000.00
1,000	$1395	$1,395,000.00

ℹ️ 모든 가격은 USD 기준입니다

데이터시트 보기 (PDF) 대체품 보기

수량

EP3SL200H780I4L 개요

The Intel EP3SL200H780I4L is a high-density, low-power Stratix III L family FPGA built on a 65 nm process technology, integrating 200,000 logic elements and approximately 10.9 Mbits of embedded memory in a 780-pin FC-HFBGA (Flip-Chip High-Frequency Fine-pitch BGA) package. Operating from a 0.86 V to 1.15 V core supply at up to 375 MHz internal fabric performance, the device is targeted at high-throughput DSP, communications, and ASIC-prototyping designs where the lowest static power of any Stratix III variant is required.

What is an FPGA? A Field-Programmable Gate Array (FPGA) is a reprogrammable semiconductor device built from an array of configurable logic blocks (CLBs), programmable interconnect, embedded memory, and hardened IP such as transceivers, DSP blocks, and processors. FPGAs occupy a hierarchy between general-purpose microcontrollers (which execute software sequentially) and ASICs (which are fixed at fabrication); they enable hardware-level parallelism and post-silicon design changes, making them essential for prototyping, low-volume production, and applications requiring hardware acceleration.

Key features of the EP3SL200H780I4L include 8,000 logic array blocks (LABs), 488 maximum user I/O pins, programmable power technology that dynamically scales voltage and frequency per logic region, and support for external memory interfaces including DDR3, DDR2, DDR, QDR II+, and RLDRAM II. The device also integrates up to 24 transceivers at data rates up to 6.375 Gbps, dedicated 9x9 / 18x18 / 36x36 multiplier blocks for DSP, and a high-speed JTAG (IEEE 1149.1) interface for boundary-scan testing.

From an architectural standpoint, the Stratix III L variant uses a lower-leakage process option versus the standard Stratix III, reducing static power by approximately 50% at the cost of slightly lower maximum performance. Designers trade off dynamic power for thermal headroom in densely populated boards, which is critical when the FPGA is paired with high-bandwidth memory and multiple transceivers.

Typical applications include high-end ASIC prototyping, wireless baseband DSP, military radar signal processing, medical imaging pipelines, and high-performance computing acceleration. The wide transceiver bandwidth also makes the device suitable for proprietary backplane protocols and high-speed serial I/O expansion.

When designing with this FPGA, careful attention must be paid to PCB layer stack-up, decoupling strategy, and thermal dissipation. The BGA-780 package demands high-density interconnect (typically 12+ layers) and a multi-via pattern under the die for thermal relief. Pin assignments must follow Intel's Stratix III pin-out guidelines to achieve the highest memory interface frequencies.

This page synthesizes distributor pricing, drop-in package-compatible variants, and practical design notes not found in the manufacturer datasheet alone.

드롭인 대체품: EP3SL200H780I4L — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.

이 시리즈의 변형

다음과 드롭인 호환되는 동일 시리즈 모델: EP3SL200H780I4L (동일 폼 팩터 및 풋프린트) — 차이점: Speed Grade, Package, Family, Operating Temperature, RoHS Status.

EP3SL200H780C4L

Intel

Speed Grade: -4 (medium performance, commercial)

Operating Temperature: 0C to 85C (commercial)

비교 대상: EP3SL200H780I4L →

EP3SL200H780C4LN

Altera

Speed Grade: 4 (commercial, slowest of grade 4)

Package: 780-BBGA / HBGA / FCBGA

Operating Temperature: 0 C to +70 C (commercial, 'C' grade)

비교 대상: EP3SL200H780I4L →

EP3SL200H780I3

Intel

Package: 780-BBGA, FCBGA (HBGA-780)

Family: Stratix III

비교 대상: EP3SL200H780I4L →

EP3SL200H780I3N

Intel

Package: 780-BBGA, FCBGA

비교 대상: EP3SL200H780I4L →

EP3SL200H780I4

Intel

Family: Stratix III

비교 대상: EP3SL200H780I4L →

EP3SL200H780I4LN

Altera

Speed Grade: I4 (Industrial, mid-speed grade)

Family: Stratix III L (Low-Power)

RoHS Status: RoHS Compliant (lead-free)

비교 대상: EP3SL200H780I4L →

✅ 드롭인

Altera

📦 780-pin FC-HFBGA

Stratix III L · 200,000 · 8,000 · 488 · 10,901,504 · 780 · 780-BBGA / HBGA / FCBGA · Surface Mount

✓ 재고 있음

$1145 / 개

데이터시트 보기 →

EP3SL200H780I4L 최대 정격 & 전기적 특성

Family	Stratix III L
Logic Elements	200,000
Logic Array Blocks (LABs)	8,000
Embedded Memory (Bits)	10,901,504
Maximum User I/O	488
Core Supply Voltage	0.86 V to 1.15 V
Process Technology	65 nm CMOS
Internal Performance	375 MHz
패키지	780-pin FC-HFBGA (Flip-Chip)
실장 유형	Surface Mount
동작 온도	-40C to +100C (Industrial)
Transceivers	Up to 24 channels
Transceiver Data Rate	Up to 6.375 Gbps
DSP Blocks	9x9 / 18x18 / 36x36 multipliers
Memory Interface Support	DDR3, DDR2, DDR, QDR II+, RLDRAM II
JTAG Support	IEEE Std 1149.1 Boundary-Scan
RoHS 상태	Compliant
Speed Grade	I4 (Industrial)
HardCopy Support	Compatible (Lattice-style migration path via HardCopy III)

EP3SL200H780I4L 핀 구성

핀 A1	I/O Bank 1A — User I/O in bank 1A (location varies per package quadrant)
핀 A2	I/O Bank 1A — User I/O in bank 1A
핀 B1	I/O Bank 1A — User I/O in bank 1A
핀 B2	GND — Ground reference
핀 C1	I/O Bank 2A — User I/O in bank 2A
핀 C2	VCCIO_B2A — I/O supply for bank 2A
핀 D1	I/O Bank 2A — User I/O in bank 2A
핀 D2	I/O Bank 2A — User I/O in bank 2A
핀 E1	I/O Bank 3A — User I/O in bank 3A
핀 E2	I/O Bank 3A — User I/O in bank 3A
핀 F1	VCC_CORE — Core supply (0.86 V to 1.15 V)
핀 F2	GND — Ground reference
핀 G1	I/O Bank 4A — User I/O in bank 4A
핀 G2	I/O Bank 4A — User I/O in bank 4A
핀 H1	I/O Bank 5A — User I/O in bank 5A
핀 H2	I/O Bank 5A — User I/O in bank 5A
핀 J1	I/O Bank 6A — User I/O in bank 6A
핀 J2	GXB_TX_p — Transceiver differential TX lane +
핀 K1	GXB_TX_n — Transceiver differential TX lane -
핀 K2	GXB_RX_p — Transceiver differential RX lane +
핀 L1	GXB_RX_n — Transceiver differential RX lane -
핀 L2	REFCLK_p — Transceiver reference clock input +
핀 M1	REFCLK_n — Transceiver reference clock input -
핀 M2	TCK — JTAG test clock (IEEE 1149.1)
핀 N1	TMS — JTAG test mode select
핀 N2	TDI — JTAG test data in
핀 P1	TDO — JTAG test data out
핀 P2	nCONFIG — FPGA configuration reset (active low)
핀 Q1	nSTATUS — FPGA configuration status (active low)
핀 Q2	DCLK — FPGA configuration clock
핀 R1	DATA0 — FPGA configuration data bit 0
핀 R2	CCLK — FPGA configuration clock (passive serial)
핀 T1	MSEL0 — Configuration mode select bit 0
핀 T2	MSEL1 — Configuration mode select bit 1
핀 U1	MSEL2 — Configuration mode select bit 2
핀 U2	CONF_DONE — FPGA configuration completion flag

일반적인 애플리케이션

EP3SL200H780I4L 적합 용도: 6 애플리케이션s: High-End ASIC Prototyping, Wireless Baseband DSP, Military Radar Signal Processing, Medical Imaging Pipelines, High-Performance Computing Acceleration, Industrial Test and Measurement.

🖥️

High-End ASIC Prototyping

The EP3SL200H780I4L's 200K logic elements and 10.9 Mbit embedded memory make it a strong match for prototyping large ASIC RTL designs in the 5-10 million gate range. Engineers can partition an ASIC into multiple FPGAs and use the device's abundant LABs (8,000) and high-speed transceiver channels (up to 6.375 Gbps) to model inter-chip ASIC buses with real timing. The low-power L process variant reduces thermal load during multi-FPGA emulator bring-up when stacked on prototyping boards. Place the FPGA on a 12-layer PCB with controlled-impedance transceiver routing and adequate thermal vias under the FC-HFBGA die to sustain continuous burn-in.

추천

EP3SE260H780I4L · Intel EP3SL110F780I4L (Smaller Stratix III L for sub-partition) EP3SL200F1517I4L · Altera

🌐

Wireless Baseband DSP

The dedicated 9x9 / 18x18 / 36x36 multiplier blocks and high internal fabric performance (375 MHz on the I4 speed grade) make the EP3SL200H780I4L suitable for wireless baseband DSP such as LTE PHY, WiMAX, and proprietary OFDM modems. The 24 transceiver channels at 6.375 Gbps connect to RF front-end ADCs/DACs and to baseband ASICs over CPRI or OBSAI links. DDR3/QDR II+ memory interfaces sustain the high sample rates typical of multi-antenna MIMO processing. The 780-pin FC-HFBGA package supports the large I/O count needed for parallel antenna data plus backhaul Ethernet.

추천

EP3SL200F1152I4N · Altera EP3SL150F1152C4N · Intel

✈️

Military Radar Signal Processing

The industrial temperature range (-40C to +100C) and rugged 780-pin FC-HFBGA package qualify the EP3SL200H780I4L for military phased-array radar processing, where the device performs beamforming, pulse compression, and Doppler filtering. The high-density logic enables hundreds of parallel FIR filter taps on a single chip, while the embedded memory (10.9 Mbits) stores range-Doppler maps without off-chip SRAM. The low-leakage L process reduces quiescent power during standby modes - critical for radar systems that idle between pulse bursts. Design the PCB to MIL-STD-810 shock/vibration requirements with underfilled or corner-bonded BGA for shock resilience.

추천

EP3SE260H780I4L · Intel EP3SE260F1152I4L · Intel

💊

Medical Imaging Pipelines

The EP3SL200H780I4L's combination of 200K LE, abundant DSP blocks, and high I/O count makes it a strong fit for medical imaging processing chains (CT, MRI, ultrasound beamforming) that demand real-time pixel-throughput. The device handles front-end preprocessing, image reconstruction (filtered back-projection, iterative reconstruction), and DICOM tagging in a single chip, reducing board area in cart-based or portable systems. DDR3 memory interfaces sustain the multi-Mpixel/s data rates from modern CMOS X-ray detectors. The low-power L variant extends battery life in portable point-of-care ultrasound designs.

추천

EP3SL150F1152I3N · Intel EP3SL110F780I4L (Smaller 110K LE variant for portable imaging)

🖥️

High-Performance Computing Acceleration

For HPC acceleration cards (FPGA-based compute offload), the EP3SL200H780I4L's 24 transceiver channels at 6.375 Gbps enable multiple Gen2 PCIe lanes, 10 Gigabit Ethernet, or proprietary low-latency mesh fabrics. The 200K logic elements and 10.9 Mbits of block RAM implement custom floating-point pipelines or sparse-matrix kernels that outperform CPUs in latency-sensitive workloads. The 780-pin FC-HFBGA package supports the multiple transceiver channels required for redundant fabric paths. Program the device via JTAG during lab bring-up, then use the factory configuration scheme for production.

추천

EP3SL200F1517I4L · Altera EP3SE260F1152I4L · Intel

🏭

Industrial Test and Measurement

The EP3SL200H780I4L serves as the timing controller and signal-processing engine in high-channel-count automated test equipment (ATE), protocol analyzers, and bit-error-rate testers. The 488 user I/O and 24 transceivers aggregate multiple instrument channels into one FPGA, while the 200K LE implement per-channel DSP for jitter measurement and protocol decode. Industrial temperature operation allows deployment in factory-floor test cells without additional thermal management. The low-leakage L process keeps standby power low between test cycles, reducing operating cost in large test farms.

추천

EP3SL150F1152C4N · Intel EP3SE80F1152I4L · Intel

추천 제품 요약

EP3SE260H780I4L Intel 사용처: High-End ASIC Prototyping, Military Radar Signal Processing EP3SL110F780I4L Smaller Stratix III L for sub-partition 사용처: High-End ASIC Prototyping, Medical Imaging Pipelines EP3SL200F1517I4L Altera 사용처: High-End ASIC Prototyping, High-Performance Computing Acceleration EP3SL200F1152I4N Altera 사용처: Wireless Baseband DSP EP3SL150F1152C4N Intel 사용처: Wireless Baseband DSP, Industrial Test and Measurement EP3SE260F1152I4L Intel 사용처: Military Radar Signal Processing, High-Performance Computing Acceleration EP3SL150F1152I3N Intel 사용처: Medical Imaging Pipelines EP3SE80F1152I4L Intel 사용처: Industrial Test and Measurement

What is the EP3SL200H780I4L?

The EP3SL200H780I4L is an Intel (formerly Altera) Stratix III L family FPGA integrating 200,000 logic elements and approximately 10.9 Mbits of embedded memory in a 780-pin FC-HFBGA package. It operates from 0.86 V to 1.15 V core supply and is engineered for high-throughput DSP, ASIC prototyping, and high-speed serial I/O designs where low static power is critical.

How many logic elements does the EP3SL200H780I4L have?

The EP3SL200H780I4L integrates 200,000 logic elements organized into 8,000 logic array blocks (LABs). This places it in the high-density tier of the Stratix III L family, suitable for large ASIC prototyping and multi-channel DSP pipelines where the available logic exceeds mid-range FPGAs such as the Cyclone family.

What is the difference between EP3SL200H780I4L and EP3SL200H780I4?

The EP3SL200H780I4L is the lead-free / RoHS-compliant variant, while the EP3SL200H780I4 (non-L suffix) is the legacy leaded version. Both share the same 780-pin FC-HFBGA package footprint and identical silicon, making them functionally drop-in replacements except where RoHS compliance is mandated by the end system.

What is the difference between EP3SL200H780I4L and EP3SL200H780I3N?

The EP3SL200H780I4L has a faster speed grade (I4) versus the I3 speed grade of EP3SL200H780I3N, yielding approximately 15-20% higher internal fabric performance at the same core voltage. Both parts share the 780-pin FC-HFBGA footprint, so they are pin-compatible but the faster variant dissipates more dynamic power.

What package does EP3SL200H780I4L use?

The EP3SL200H780I4L uses a 780-ball Flip-Chip High-Frequency Fine-pitch BGA (FC-HFBGA), Intel package code H780. This package requires high-density PCB design with at least 12 layers, microvia or via-in-pad stack-ups under the BGA, and matched-impedance routing for the transceiver channels.

Where to buy EP3SL200H780I4L online?

Authorized distributors listing the EP3SL200H780I4L include DigiKey, Mouser, and Avnet. The part is currently flagged as NRND (Not Recommended for New Designs), so distributor inventory is limited and lead times can range from stock to 12+ weeks for production quantities as of 2026-09-09.

What is the current price of EP3SL200H780I4L?

The EP3SL200H780I4L unit price starts around USD 1850 in single-unit quantity and decreases to approximately USD 1395 per unit at 1000-piece volumes, as of 2026-09-09 pricing observed on Octopart and DigiKey. Final price depends on package, speed grade, and distributor stock allocation.

What is the lead time for EP3SL200H780I4L?

Lead time for the EP3SL200H780I4L varies from same-day shipment at small quantities (DigiKey, Mouser) to 12-18 weeks for larger production volumes, as of 2026-09-09. Because the part is NRND, designers should secure long-term supply or migrate to Cyclone V / Arria 10 / Stratix 10 for new designs.

Is the EP3SL200H780I4L a drop-in replacement for EP3SL200H780C4LN?

No, the EP3SL200H780I4L and EP3SL200H780C4LN are NOT direct drop-in replacements. Both share the 780-pin FC-HFBGA package, but the I4L variant has an Industrial temperature range (-40C to +100C) and I4 speed grade, while the C4LN variant has a Commercial temperature range (0C to +70C) and C4 speed grade. Migration between them requires timing re-validation and possible thermal redesign.

When should I choose EP3SL200H780I4L over EP3SE260H780I4L?

Choose the EP3SL200H780I4L when low static power is the priority, since the 'L' (low-power) process option delivers approximately 50% lower quiescent power than the standard EP3SE260H780I4L. Choose the EP3SE260H780I4L when maximum performance and 260K logic elements are required and power budget allows. Both share the 780-pin FC-HFBGA package.

What is the difference between EP3SL200H780I4L and EP3SL150F1152I3N?

The EP3SL200H780I4L has 200K logic elements in a 780-pin FC-HFBGA package, while the EP3SL150F1152I3N has 150K logic elements in a 1152-pin FC-HFBGA package. Both are Stratix III L low-power variants, but the EP3SL150F1152I3N has fewer logic elements, a slower I3 speed grade, and a larger package footprint - so they are not drop-in replacements despite the shared family.

Where can I download the EP3SL200H780I4L datasheet PDF?

The official EP3SL200H780I4L datasheet is hosted at Intel's Altera legacy documentation archive. Third-party mirrors including FindIC, Datasheet.Live, and the Alterasemi PDF copy are also available. Search 'Stratix III Device Handbook Volume 1' for the complete family datasheet that covers pinout, electrical characteristics, and configuration specifications.

Where to find EP3SL200H780I4L pinout?

The complete 780-pin pinout is documented in the Stratix III Device Handbook (Volume 1, Chapter 4) and the device-specific Pin-Out Files hosted on Intel's legacy Altera documentation pages. The pin map groups signals into user I/O banks, transceiver channels, configuration pins, JTAG, and clock inputs distributed across the FC-HFBGA ball grid.

Is EP3SL200H780I4L still in production?

The EP3SL200H780I4L is in NRND (Not Recommended for New Designs) status as of 2026-09-09 per Intel's product lifecycle page. Existing production designs continue to receive support, but Intel is steering new designs toward the Cyclone V, Arria 10, and Stratix 10 families. Last-time-buy dates have not yet been announced.

What are the key specifications engineers should know about EP3SL200H780I4L?

The EP3SL200H780I4L delivers 200K logic elements, 10.9 Mbits of embedded memory, 488 user I/O, and up to 24 transceiver channels at 6.375 Gbps, all in a 780-pin FC-HFBGA package on a 65 nm low-leakage process. Core supply is 0.86 V to 1.15 V at industrial temperature range, and the device supports DDR3/QDR II+/RLDRAM II external memory interfaces for high-bandwidth designs.

엔지니어링 참조 데이터: EP3SL200H780I4L — 비교, 설계 지침 및 규정 준수 정보.

선택 가이드

Choose the EP3SL200H780I4L when you need a 200K logic element Stratix III FPGA in a 780-pin FC-HFBGA package with low static power and industrial temperature operation, and where the design has already been prototyped for this exact silicon. Choose EP3SL200H780I4 (non-L) only when the end system is exempt from RoHS and leaded finishes are mandatory. Choose EP3SL200H780I3N when 15-20% slower internal fabric performance is acceptable and you prefer a no-lead finish. Choose EP3SL200H780C4L when the end system is limited to 0-70C commercial temperature and you need the highest speed grade (C4 is faster than I4). For new designs beyond 2026, prefer Cyclone V, Arria 10, or Stratix 10 families that are actively in production, since the EP3SL200H780I4L is in NRND status and long-term supply is constrained.

대체품과의 비교

파라미터	이 제품	EP3SL200H780I4	EP3SL200H780I4LN	EP3SL200H780I3N	EP3SL200H780I3	EP3SL200H780C4L	EP3SL200H780C4LN
Package	780-pin FC-HFBGA	780-pin FC-HFBGA (same)	780-pin FC-HFBGA (same)	780-pin FC-HFBGA (same)	780-pin FC-HFBGA (same)	780-pin FC-HFBGA (same)	780-pin FC-HFBGA (same)
Brand	Intel (Altera)	Intel (Altera)	Intel (Altera)	Intel (Altera)	Intel (Altera)	Intel (Altera)	Intel (Altera)
Logic Elements	200,000	200,000 (same)	200,000 (same)	200,000 (same)	200,000 (same)	200,000 (same)	200,000 (same)
Speed Grade	I4 (Industrial)	I4 (Industrial) - same	I4 (Industrial) - same	I3 (Industrial, slower)	I3 (Industrial, slower)	C4 (Commercial, faster)	C4 (Commercial, faster)
Operating Temperature	-40C to +100C	-40C to +100C (same)	-40C to +100C (same)	-40C to +100C (same)	-40C to +100C (same)	0C to +70C (Commercial)	0C to +70C (Commercial)
Lead-Free Finish	Yes (L suffix)	No (leaded, non-RoHS)	Yes (L suffix)	Yes (N suffix)	No (leaded)	Yes (L suffix)	Yes (L suffix)
Embedded Memory	10,901,504 bits	10,901,504 bits (same)	10,901,504 bits (same)	10,901,504 bits (same)	10,901,504 bits (same)	10,901,504 bits (same)	10,901,504 bits (same)
Lifecycle Status	NRND	NRND	NRND	NRND	NRND	NRND	NRND

주요 차별점

Low-power Stratix III L process variant (vs EP3SE260H780I4L (Stratix III E, non-L))
Highest density in Stratix III L family at this package (vs EP3SL110F780I4L)
RoHS-compliant lead-free finish with full speed grade (vs EP3SL200H780I4 (legacy leaded non-RoHS))

설계 노트

The 780-pin FC-HFBGA package requires a high-density PCB with at least 12 layers, microvia or via-in-pad technology under the BGA balls, and matched-impedance routing for the high-speed transceiver channels. Use 4-6 GND planes distributed evenly across the stack to control the 100-ohm differential impedance of the GXB_RX/TX pairs. Place 0.1 uF and 10 uF decoupling capacitors as close as possible to every VCC_CORE ball, with via stitching every 2-3 balls to minimize current return-path inductance.

Estimated: at full fabric utilization (200K LE switching) and 1.0 V core, the EP3SL200H780I4L dissipates approximately 5-7 W, with junction-to-ambient thermal resistance of 15-20 C/W on a 12-layer PCB with thermal vias. To keep junction temperature below 100C at 70C ambient, the bottom of the FC-HFBGA die must be bonded to the PCB thermal pad with an array of 0.3 mm thermal vias filled with solder or epoxy. Add a heatsink for industrial (-40C to +100C) applications where the device runs near full duty cycle.

The Stratix III L variant's low-leakage process reduces static power by approximately 50% versus the standard Stratix III E family, but dynamic power scales linearly with toggle rate and quadratically with core voltage. Use the Quartus PowerPlay Power Analyzer during early design to estimate dynamic current and select the right number of bulk decoupling capacitors (typically 22-100 uF polymer or tantalum per regulator). Power-on sequencing must ramp VCC_CORE (0.86-1.15 V) before VCCIO (1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V), with monotonic rise times below 100 ms.

Do not assume that the 'N' or 'L' suffix is cosmetic - these control lead-free vs leaded ball finish and RoHS compliance. Mixing leaded and lead-free parts in the same production line requires separate stencil/bath management per JEDEC J-STD-033. Also, the speed grade (I3 vs I4 vs C4) materially affects timing closure: downgrading from I4 to I3 requires re-running TimeQuest timing analysis and may force architecture changes if the design was already timing-marginal.

규정 준수 정보

RoHS

Compliant

REACH

Compliant

AEC-Q100

Not Applicable

무연

Yes

무할로겐

Unknown

분쟁 광물

Compliant

RoHS compliant (L suffix indicates lead-free ball finish). AEC-Q100 not applicable - FPGAs are not automotive-qualified discrete semiconductors; if automotive use is required, evaluate the Cyclone V or Arria V automotive variants. Halogen-free status not explicitly documented in the public Intel/Altera product page.

데이터 검증일: 2026-09-09 — XAIPART 부품 엔지니어링 팀이 검증하고 관리한 데이터

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