EPM9560RC208-4 - MAX 9000 CPLD 560 Macrocells | Altera
부품 번호: EPM9560RC208-4 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $88 | $880.00 |
| 100 | $78 | $7,800.00 |
| 500 | $70 | $35,000.00 |
| 1,000 | $62 | $62,000.00 |
EPM9560RC208-4 개요
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple PLDs and FPGAs in the programmable logic hierarchy. Compared to an FPGA, a CPLD provides predictable timing, instant-on behavior from EEPROM configuration cells, and high pin-to-pin performance for glue-logic, bus interfacing, and state-machine applications. The MAX 9000 family represents Altera's highest-density EEPROM CPLD generation, designed for wide bus bridging, fast address decoding, and high-speed control logic consolidation.
Key features of the EPM9560RC208-4 include 560 macrocells organized across 16 Logic Array Blocks (LABs), maximum operating frequency of 118.3 MHz, 16 dedicated input pins plus 96 I/O pins (208-pin RQFP), and a 4 ns combinatorial propagation delay (tPD). The device also provides 4 global clock inputs with programmable clock management, in-system programming via JTAG, and MultiVolt I/O supporting 5.0 V, 3.3 V, and 2.5 V interface levels to bridge multiple logic domains on a single board.
From an architectural perspective, the MAX 9000 family integrates an enhanced interconnect network called the Programmable Interconnect Array (PIA), which routes signals between LABs with predictable, deterministic timing. Each LAB contains 16 macrocells with shared expander product terms, enabling efficient implementation of wide gating functions and arithmetic logic. The 4 ns speed grade is the slowest in the family; faster -3, -2, and -1 grades are available for timing-critical designs requiring tighter propagation delay budgets.
Typical applications include PCI bus interface bridging, high-speed address decoding for microprocessors, glue-logic consolidation in telecom backplane designs, and control logic in industrial automation equipment. Designers choose the MAX 9000 family when instant-on behavior, deterministic timing, and non-volatile configuration are required without the cost or complexity of an SRAM-based FPGA.
When designing with this part, ensure 5 V VCC stability and provide a clean JTAG chain to support ISP. For new designs, prefer MAX II or MAX V devices from Intel (formerly Altera); the EPM9560RC208-4 is recommended for legacy maintenance, form-fit-function replacement, or where the original MAX 9000 design files are preserved.
This page synthesizes distributor availability, parametric alternatives, and legacy CPLD design considerations not found in the manufacturer datasheet alone, making it a practical reference for engineers maintaining installed-base MAX 9000 designs.
드롭인 대체품: EPM9560RC208-4 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EPM9560RC208-4 (동일 폼 팩터 및 풋프린트) — 차이점: Speed Grade, Package, Device Type, Pin-to-Pin Delay (tPD), Usable Gates.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EPM9560RC208-3
✅ 드롭인✓ 재고 있음
$58.5 / 개
데이터시트 보기 →EPM9560RC208-10
✅ 드롭인✓ 재고 있음
$15.4 / 개
데이터시트 보기 →EPM9560RC208-15
✅ 드롭인✓ 재고 있음
가격 문의
데이터시트 보기 →EPM9560RC208-20
✅ 드롭인✓ 재고 있음
가격 문의
데이터시트 보기 →EPM9560RC208-4 최대 정격 & 전기적 특성
| Family | MAX 9000 |
| Device | EPM9560 |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Logic Array Blocks (LABs) | 16 |
| Maximum Operating Frequency | 118.3 MHz |
| Pin-to-Pin Delay (tPD) | 4 ns |
| Speed Grade | -4 |
| Supply Voltage (VCC) | 5 V |
| 패키지 | 208-pin RQFP (Power Quad Flat Pack) |
| User I/O Pins | 96 (approx., 208-pin RQFP) |
| Dedicated Inputs | 16 |
| Programming Interface | IEEE 1149.1 JTAG (ISP) |
| Configuration Memory | EEPROM (non-volatile) |
| MultiVolt I/O | 5.0 V / 3.3 V / 2.5 V |
| 동작 온도 | 0C to +70C (commercial) |
EPM9560RC208-4 핀 구성
| 핀 1 | I/O — User I/O pin (LAB bank) |
| 핀 2 | I/O — User I/O pin (LAB bank) |
| 핀 3 | GND — Ground |
| 핀 4 | I/O — User I/O pin (LAB bank) |
| 핀 5 | I/O — User I/O pin (LAB bank) |
| 핀 6 | VCC — 5 V supply |
| 핀 7 | I/O — User I/O pin (LAB bank) |
| 핀 8 | I/O — User I/O pin (LAB bank) |
| 핀 9 | I/O — User I/O pin (LAB bank) |
| 핀 10 | GND — Ground |
| 핀 11 | I/O — User I/O pin (LAB bank) |
| 핀 12 | I/O — User I/O pin (LAB bank) |
| 핀 13 | I/O — User I/O pin (LAB bank) |
| 핀 14 | VCC — 5 V supply |
| 핀 15 | I/O — User I/O pin (LAB bank) |
| 핀 16 | I/O — User I/O pin (LAB bank) |
| 핀 17 | GND — Ground |
| 핀 18 | I/O — User I/O pin (LAB bank) |
| 핀 19 | I/O — User I/O pin (LAB bank) |
| 핀 20 | I/O — User I/O pin (LAB bank) |
| 핀 21 | VCC — 5 V supply |
| 핀 22 | I/O — User I/O pin (LAB bank) |
| 핀 23 | I/O — User I/O pin (LAB bank) |
| 핀 24 | GND — Ground |
| 핀 25 | I/O — User I/O pin (LAB bank) |
| 핀 26 | I/O — User I/O pin (LAB bank) |
| 핀 27 | I/O — User I/O pin (LAB bank) |
| 핀 28 | VCC — 5 V supply |
| 핀 29 | I/O — User I/O pin (LAB bank) |
| 핀 30 | I/O — User I/O pin (LAB bank) |
| 핀 31 | GND — Ground |
| 핀 32 | I/O — User I/O pin (LAB bank) |
| 핀 33 | I/O — User I/O pin (LAB bank) |
| 핀 34 | I/O — User I/O pin (LAB bank) |
| 핀 35 | VCC — 5 V supply |
| 핀 36 | I/O — User I/O pin (LAB bank) |
| 핀 37 | I/O — User I/O pin (LAB bank) |
| 핀 38 | GND — Ground |
| 핀 39 | I/O — User I/O pin (LAB bank) |
| 핀 40 | I/O — User I/O pin (LAB bank) |
| 핀 41 | I/O — User I/O pin (LAB bank) |
| 핀 42 | VCC — 5 V supply |
| 핀 43 | I/O — User I/O pin (LAB bank) |
| 핀 44 | I/O — User I/O pin (LAB bank) |
| 핀 45 | GND — Ground |
| 핀 46 | I/O — User I/O pin (LAB bank) |
| 핀 47 | I/O — User I/O pin (LAB bank) |
| 핀 48 | I/O — User I/O pin (LAB bank) |
| 핀 49 | VCC — 5 V supply |
| 핀 50 | I/O — User I/O pin (LAB bank) |
| 핀 51 | I/O — User I/O pin (LAB bank) |
| 핀 52 | GND — Ground |
| 핀 53 | I/O — User I/O pin (LAB bank) |
| 핀 54 | I/O — User I/O pin (LAB bank) |
| 핀 55 | I/O — User I/O pin (LAB bank) |
| 핀 56 | VCC — 5 V supply |
| 핀 57 | I/O — User I/O pin (LAB bank) |
| 핀 58 | I/O — User I/O pin (LAB bank) |
| 핀 59 | GND — Ground |
| 핀 60 | I/O — User I/O pin (LAB bank) |
| 핀 61 | I/O — User I/O pin (LAB bank) |
| 핀 62 | I/O — User I/O pin (LAB bank) |
| 핀 63 | VCC — 5 V supply |
| 핀 64 | I/O — User I/O pin (LAB bank) |
| 핀 65 | I/O — User I/O pin (LAB bank) |
| 핀 66 | GND — Ground |
| 핀 67 | I/O — User I/O pin (LAB bank) |
| 핀 68 | I/O — User I/O pin (LAB bank) |
| 핀 69 | I/O — User I/O pin (LAB bank) |
| 핀 70 | VCC — 5 V supply |
| 핀 71 | I/O — User I/O pin (LAB bank) |
| 핀 72 | I/O — User I/O pin (LAB bank) |
| 핀 73 | GND — Ground |
| 핀 74 | I/O — User I/O pin (LAB bank) |
| 핀 75 | I/O — User I/O pin (LAB bank) |
| 핀 76 | I/O — User I/O pin (LAB bank) |
| 핀 77 | VCC — 5 V supply |
| 핀 78 | I/O — User I/O pin (LAB bank) |
| 핀 79 | I/O — User I/O pin (LAB bank) |
| 핀 80 | GND — Ground |
| 핀 81 | I/O — User I/O pin (LAB bank) |
| 핀 82 | I/O — User I/O pin (LAB bank) |
| 핀 83 | I/O — User I/O pin (LAB bank) |
| 핀 84 | VCC — 5 V supply |
| 핀 85 | I/O — User I/O pin (LAB bank) |
| 핀 86 | I/O — User I/O pin (LAB bank) |
| 핀 87 | GND — Ground |
| 핀 88 | I/O — User I/O pin (LAB bank) |
| 핀 89 | I/O — User I/O pin (LAB bank) |
| 핀 90 | I/O — User I/O pin (LAB bank) |
| 핀 91 | VCC — 5 V supply |
| 핀 92 | I/O — User I/O pin (LAB bank) |
| 핀 93 | I/O — User I/O pin (LAB bank) |
| 핀 94 | GND — Ground |
| 핀 95 | I/O — User I/O pin (LAB bank) |
| 핀 96 | I/O — User I/O pin (LAB bank) |
| 핀 97 | I/O — User I/O pin (LAB bank) |
| 핀 98 | VCC — 5 V supply |
| 핀 99 | I/O — User I/O pin (LAB bank) |
| 핀 100 | I/O — User I/O pin (LAB bank) |
| 핀 101 | GND — Ground |
| 핀 102 | I/O — User I/O pin (LAB bank) |
| 핀 103 | I/O — User I/O pin (LAB bank) |
| 핀 104 | I/O — User I/O pin (LAB bank) |
| 핀 105 | VCC — 5 V supply |
| 핀 106 | I/O — User I/O pin (LAB bank) |
| 핀 107 | I/O — User I/O pin (LAB bank) |
| 핀 108 | GND — Ground |
| 핀 109 | I/O — User I/O pin (LAB bank) |
| 핀 110 | I/O — User I/O pin (LAB bank) |
| 핀 111 | I/O — User I/O pin (LAB bank) |
| 핀 112 | VCC — 5 V supply |
| 핀 113 | I/O — User I/O pin (LAB bank) |
| 핀 114 | I/O — User I/O pin (LAB bank) |
| 핀 115 | GND — Ground |
| 핀 116 | I/O — User I/O pin (LAB bank) |
| 핀 117 | I/O — User I/O pin (LAB bank) |
| 핀 118 | I/O — User I/O pin (LAB bank) |
| 핀 119 | VCC — 5 V supply |
| 핀 120 | I/O — User I/O pin (LAB bank) |
| 핀 121 | I/O — User I/O pin (LAB bank) |
| 핀 122 | GND — Ground |
| 핀 123 | I/O — User I/O pin (LAB bank) |
| 핀 124 | I/O — User I/O pin (LAB bank) |
| 핀 125 | I/O — User I/O pin (LAB bank) |
| 핀 126 | VCC — 5 V supply |
| 핀 127 | I/O — User I/O pin (LAB bank) |
| 핀 128 | I/O — User I/O pin (LAB bank) |
| 핀 129 | GND — Ground |
| 핀 130 | I/O — User I/O pin (LAB bank) |
| 핀 131 | I/O — User I/O pin (LAB bank) |
| 핀 132 | I/O — User I/O pin (LAB bank) |
| 핀 133 | VCC — 5 V supply |
| 핀 134 | I/O — User I/O pin (LAB bank) |
| 핀 135 | I/O — User I/O pin (LAB bank) |
| 핀 136 | GND — Ground |
| 핀 137 | I/O — User I/O pin (LAB bank) |
| 핀 138 | I/O — User I/O pin (LAB bank) |
| 핀 139 | I/O — User I/O pin (LAB bank) |
| 핀 140 | VCC — 5 V supply |
| 핀 141 | I/O — User I/O pin (LAB bank) |
| 핀 142 | I/O — User I/O pin (LAB bank) |
| 핀 143 | GND — Ground |
| 핀 144 | I/O — User I/O pin (LAB bank) |
| 핀 145 | I/O — User I/O pin (LAB bank) |
| 핀 146 | I/O — User I/O pin (LAB bank) |
| 핀 147 | VCC — 5 V supply |
| 핀 148 | I/O — User I/O pin (LAB bank) |
| 핀 149 | I/O — User I/O pin (LAB bank) |
| 핀 150 | GND — Ground |
| 핀 151 | I/O — User I/O pin (LAB bank) |
| 핀 152 | I/O — User I/O pin (LAB bank) |
| 핀 153 | I/O — User I/O pin (LAB bank) |
| 핀 154 | VCC — 5 V supply |
| 핀 155 | I/O — User I/O pin (LAB bank) |
| 핀 156 | I/O — User I/O pin (LAB bank) |
| 핀 157 | GND — Ground |
| 핀 158 | I/O — User I/O pin (LAB bank) |
| 핀 159 | I/O — User I/O pin (LAB bank) |
| 핀 160 | I/O — User I/O pin (LAB bank) |
| 핀 161 | VCC — 5 V supply |
| 핀 162 | I/O — User I/O pin (LAB bank) |
| 핀 163 | I/O — User I/O pin (LAB bank) |
| 핀 164 | GND — Ground |
| 핀 165 | I/O — User I/O pin (LAB bank) |
| 핀 166 | I/O — User I/O pin (LAB bank) |
| 핀 167 | I/O — User I/O pin (LAB bank) |
| 핀 168 | VCC — 5 V supply |
| 핀 169 | I/O — User I/O pin (LAB bank) |
| 핀 170 | I/O — User I/O pin (LAB bank) |
| 핀 171 | GND — Ground |
| 핀 172 | I/O — User I/O pin (LAB bank) |
| 핀 173 | I/O — User I/O pin (LAB bank) |
| 핀 174 | I/O — User I/O pin (LAB bank) |
| 핀 175 | VCC — 5 V supply |
| 핀 176 | TDI — JTAG Test Data In |
| 핀 177 | TMS — JTAG Test Mode Select |
| 핀 178 | TCK — JTAG Test Clock |
| 핀 179 | TDO — JTAG Test Data Out |
| 핀 180 | I/O — User I/O pin (LAB bank) |
| 핀 181 | GND — Ground |
| 핀 182 | I/O — User I/O pin (LAB bank) |
| 핀 183 | I/O — User I/O pin (LAB bank) |
| 핀 184 | VCC — 5 V supply |
| 핀 185 | INPUT/GCLK1 — Dedicated input / global clock 1 |
| 핀 186 | INPUT/GCLK2 — Dedicated input / global clock 2 |
| 핀 187 | INPUT/GCLK3 — Dedicated input / global clock 3 |
| 핀 188 | INPUT/GCLK4 — Dedicated input / global clock 4 |
| 핀 189 | INPUT/OE1 — Dedicated input / global OE 1 |
| 핀 190 | INPUT/OE2 — Dedicated input / global OE 2 |
| 핀 191 | INPUT/CLR — Dedicated input / global clear |
| 핀 192 | INPUT — Dedicated input |
| 핀 193 | GND — Ground |
| 핀 194 | INPUT — Dedicated input |
| 핀 195 | INPUT — Dedicated input |
| 핀 196 | INPUT — Dedicated input |
| 핀 197 | VCC — 5 V supply |
| 핀 198 | INPUT — Dedicated input |
| 핀 199 | INPUT — Dedicated input |
| 핀 200 | INPUT — Dedicated input |
| 핀 201 | INPUT — Dedicated input |
| 핀 202 | GND — Ground |
| 핀 203 | INPUT — Dedicated input |
| 핀 204 | INPUT — Dedicated input |
| 핀 205 | INPUT — Dedicated input |
| 핀 206 | VCC — 5 V supply |
| 핀 207 | INPUT — Dedicated input |
| 핀 208 | INPUT — Dedicated input |
일반적인 애플리케이션
EPM9560RC208-4 적합 용도: 6 애플리케이션s: PCI Bus Interface Bridging, High-Speed Address Decoding, Telecom Backplane Glue Logic, Industrial Automation Control Logic, Legacy Peripheral Chip Consolidation, Memory and DSP Interface Bridging.
PCI Bus Interface Bridging
The EPM9560RC208-4 is well suited for PCI bus interface bridging because its 560 macrocells and 4 ns tPD enable single-cycle address and command decoding across 32-bit PCI buses. In a typical 5 V PCI design, the device decodes C/BE and address lines while generating chip-selects for memory and peripheral devices, replacing multiple discrete 74FCT and PAL devices with one non-volatile part. The 16 dedicated inputs handle PCI clock and control signals with predictable timing, while the MultiVolt I/O simplifies bridging to 3.3 V downstream peripherals. The 4 ns grade ensures timing margin under worst-case load and temperature conditions.
추천
High-Speed Address Decoding
For high-speed microprocessor address decoding, the EPM9560RC208-4's 560 macrocells support large memory maps with multiple chip-select outputs. A typical 32-bit address decoder needs 8 to 16 product terms per chip-select; the EPM9560's 16 LABs with 16 macrocells each provide ample capacity for 12 to 24 chip-select outputs plus address-strobe gating logic. The 4 ns tPD ensures the chip-select signals arrive within the same clock cycle as the address latch, which is critical at 50 MHz and above. The non-volatile EEPROM configuration means no boot PROM is required and the design is ready at power-on.
추천
Telecom Backplane Glue Logic
In telecom backplane designs, the EPM9560RC208-4 consolidates bus arbitration, interrupt steering, and reset distribution across multiple line cards. The 208-pin RQFP package provides sufficient I/O for 96 user I/O plus 16 dedicated inputs to handle bus control signals, JTAG chain management, and inter-card communication. The MultiVolt I/O allows the device to interface between 5 V legacy cards and 3.3 V ASICs without external level shifters. The non-volatile configuration supports instant-on operation required for telecom hot-swap and redundancy architectures.
추천
Industrial Automation Control Logic
The EPM9560RC208-4 is used in industrial PLC and motor-control designs to consolidate ladder-logic-equivalent state machines, encoder-decoder logic, and safety-interlock gating. Its deterministic 4 ns tPD enables precise timing for PWM generation and servo-loop control, while the EEPROM-based configuration survives industrial EMI events that would corrupt SRAM-based devices. The 208-pin RQFP supports the I/O count required for multi-axis control with parallel encoder, limit-switch, and contactor interfaces. Designers often use the JTAG interface for in-system programming during commissioning.
추천
Legacy Peripheral Chip Consolidation
Designers use the EPM9560RC208-4 to replace multiple 22V10, 26V12, and discrete TTL/CMOS glue-logic devices in legacy designs with a single programmable part. This consolidation reduces PCB area, simplifies inventory, and improves reliability by removing dozens of solder joints. The 12,000 usable gates and 560 macrocells provide enough capacity to absorb entire schematics pages of discrete logic. The 5 V VCC and TTL-compatible I/O match the legacy signal environment, eliminating the need for voltage-translation buffers in retrofit applications.
추천
Memory and DSP Interface Bridging
The EPM9560RC208-4 bridges asynchronous SRAM, Flash, and DSP peripherals to microprocessors with deterministic timing. The 4 ns tPD enables zero-wait-state interfacing at 40 MHz bus speeds, while the 560 macrocells can implement bank-switch logic, byte-lane steering, and parity/ECC handling for 32-bit memory subsystems. The device's MultiVolt I/O supports 5 V, 3.3 V, and 2.5 V signaling, simplifying designs that mix legacy and modern DSPs. The JTAG interface enables in-system programming and boundary-scan test for high-reliability applications.
추천
추천 제품 요약
엔지니어링 참조 데이터: EPM9560RC208-4 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EPM9560RC208-3 | EPM9560RC208-10 | EPM9560RC208-15 | EPM9560RC208-20 |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | 208-pin RQFP | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Macrocells | 560 | 560 | 560 | 560 | 560 |
| Pin-to-Pin Delay (tPD) | 4 ns | 3 ns (-25%) | 10 ns (+150%) | 15 ns (+275%) | 20 ns (+400%) |
| Maximum Frequency (fMAX) | 118.3 MHz | 147 MHz | 71.4 MHz | 50 MHz | 38.5 MHz |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V |
| Configuration Memory | EEPROM | EEPROM | EEPROM | EEPROM | EEPROM |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
주요 차별점
- Lowest propagation delay in the discontinued EPM9560 family (vs EPM9560RC208-20)
- Same 208-pin RQFP footprint as other EPM9560RC208 grades (vs EPM9560RC208-3)
- Non-volatile EEPROM configuration eliminates boot PROM (vs SRAM-based FPGAs)
설계 노트
The EPM9560RC208-4 operates from a 5 V VCC supply with multiple VCC and GND pins distributed around the 208-pin RQFP package for power integrity. Decouple each VCC pin with a 0.1 uF ceramic capacitor placed as close as possible to the package, and add a bulk 10 to 47 uF tantalum or aluminum electrolytic capacitor near the device. The MultiVolt I/O pins draw power from VCCIO rails, which can be set independently to 5.0 V, 3.3 V, or 2.5 V; ensure each VCCIO bank is properly decoupled to prevent logic errors during I/O switching.
Do not use the EPM9560RC208-4 in new designs: the MAX 9000 family is obsolete and Intel/Altera recommends migrating to MAX II, MAX V, or MAX 10 CPLDs. For legacy board repair or form-fit-function replacement, verify exact speed-grade compatibility because the -4 has tighter timing than the more available -20 grade. Also note that the original 208-pin ceramic CQFP was discontinued; only the 208-pin RQFP package remains form-fit-function equivalent, so legacy CQFP boards must be respun for RQFP footprints.
The EPM9560RC208-4's deterministic 4 ns tPD and PIA-based interconnect give predictable timing, but simultaneous switching of multiple I/O pins can cause ground bounce on shared GND pins. Use a 4-layer PCB with dedicated ground and power planes, and place series resistors (22 to 33 ohm) on high-speed outputs to dampen reflections. The MultiVolt I/O banks must not be mixed across voltage domains on the same physical bank; assign each bank to a single VCCIO voltage to prevent contention.
규정 준수 정보
Compliance status not provided in Verified Web Data. EPM9560 family was originally specified before RoHS mandates; later production runs may have transitioned to lead-free but specific compliance is not confirmed in the available data.