SI1553DL-T1-E3 - 20V Complementary N/P MOSFET, SC-70-6 | Vishay
부품 번호: SI1553DL-T1-E3 ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $0.55 | $0.55 |
| 10 | $0.48 | $4.80 |
| 100 | $0.36 | $36.00 |
| 500 | $0.28 | $140.00 |
| 1,000 | $0.22 | $220.00 |
SI1553DL-T1-E3 개요
A MOSFET array (also called a MOSFET pair or dual MOSFET) is a single-package device that integrates two discrete MOSFETs - typically one N-channel and one P-channel - into a common footprint. MOSFET arrays belong to the broader category of discrete semiconductors, specifically the power MOSFET subfamily, which in turn is part of the transistor family and the broader semiconductor device hierarchy. By combining both polarities in one IC, designers can build complementary switches, level shifters, load switches, and small-signal analog stages without placing two separate SOT-23 or SC-70 parts.
Key features include a 1 V typical gate threshold, low on-resistance of 5 Ω at VGS = 2.5 V, fast switching, and a compact 6-lead SC-70 (SC-88 / SOT-363) outline. The TrenchFET process geometry shrinks the channel resistance per unit area, allowing the device to deliver higher current than older planar MOSFET generations within the same die footprint.
The complementary N/P architecture lets designers replace two discrete transistors - one N-channel and one P-channel - with a single part, simplifying PCB layout and reducing BOM count. This is particularly useful where space is constrained and the two devices must be thermally and electrically matched.
Typical applications include load switching in portable and battery-powered devices, level translation between 1.8 V/3.3 V logic domains, power-rail gating in smartphones and wearables, LED driver stages, and small-signal analog switching. The 2.5 V gate threshold allows direct interface with sub-3 V microcontrollers without a separate gate driver.
When designing with the SI1553DL-T1-E3, observe standard MOSFET handling precautions: gate oxide breakdown voltage is 8 V, so do not exceed this rating under transient conditions, and ensure the gate-source voltage stays within datasheet limits. Use a gate resistor in the 10 Ω to 100 Ω range to control ringing and EMI during high-speed switching.
This page consolidates distributor pricing, drop-in compatible alternatives, and PCB-level design notes in one place - a synthesis not found in the standalone Vishay datasheet.
드롭인 대체품: SI1553DL-T1-E3 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: SI1553DL-T1-E3 (동일 폼 팩터 및 풋프린트) — 차이점: Operating Temperature Range, Package, Configuration, Drain-Source Voltage (VDS), Halogen-Free.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
SI1553DL-T1-GE3
✅ 드롭인✓ 재고 있음
$0.14 / 개
데이터시트 보기 →SI1555DL-T1-E3
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SI1563DH-T1-E3
✅ 드롭인✓ 재고 있음
$0.29 / 개
데이터시트 보기 →SI1563EDH-T1-E3
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SI1551DL-T1-E3
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SI1553DL-T1-E3 최대 정격 & 전기적 특성
| Manufacturer | Vishay Siliconix |
| Configuration | N-Channel + P-Channel (Complementary Pair) |
| Drain-Source Voltage (VDS) | 20 V |
| Gate-Source Voltage (VGS) | ±8 V |
| Continuous Drain Current N-Ch (ID) | 660 mA |
| Continuous Drain Current P-Ch (ID) | 410 mA |
| On-Resistance N-Ch (RDS(on)) | 5 Ω typical @ VGS = 2.5 V |
| Gate Threshold Voltage (VGS(th)) | 0.9 V typical |
| Total Power Dissipation | 270 mW |
| 동작 온도 범위 | -55 °C to +150 °C |
| 패키지 | SC-70-6 (SOT-363 / SC-88) |
| 실장 유형 | Surface Mount |
| Technology | TrenchFET |
| Halogen-Free Option | Yes (per IEC 61249-2-21) |
| RoHS 상태 | Compliant (RoHS Directive 2002/95/EC) |
| Lead (Pb) Content | Lead-free (E3 suffix) |
SI1553DL-T1-E3 핀 구성
| 핀 1 | S1 — Source 1 (N-channel) |
| 핀 2 | G1 — Gate 1 (N-channel) |
| 핀 3 | D2 — Drain 2 (P-channel) |
| 핀 4 | S2 — Source 2 (P-channel) |
| 핀 5 | D1 — Drain 1 (N-channel) |
| 핀 6 | G2 — Gate 2 (P-channel) |
안전 동작 영역 - N-Channel (DC)
일반적인 애플리케이션
SI1553DL-T1-E3 적합 용도: 6 애플리케이션s: Load Switch in Portable Devices, Logic Level Translation (1.8V to 3.3V), Battery Protection and Reverse Polarity Blocking, LED Driver Switch (PWM Dimming), Analog Switch and Signal Multiplexing, IoT and Wearable Sensor Power Gating.
Load Switch in Portable Devices
The SI1553DL-T1-E3 is well suited as a discrete load switch in smartphones, tablets, and wearables because its 0.9 V typical gate threshold and 5 Ω RDS(on) at VGS = 2.5 V let the device switch directly from a 2.5 V or 3.3 V GPIO without a gate driver. The 660 mA N-channel and 410 mA P-channel ratings cover most sub-rail power gating for sensors, display backlights, and sub-PMIC rails. The 270 mW power dissipation envelope keeps self-heating negligible for typical 100 mA load currents. Performance consideration: place the device near the load to minimize trace inductance, and add a 100 kΩ gate pull-down to ensure the load is off during microcontroller reset. Compared to using two discrete SOT-23 MOSFETs, the SI1553DL-T1-E3 halves the PCB footprint and removes the need to match two separate thermal curves.
추천
Logic Level Translation (1.8V to 3.3V)
The complementary N/P architecture of the SI1553DL-T1-E3 makes it a strong fit for unidirectional logic-level translation between 1.8 V and 3.3 V domains. Configure the N-channel as the pull-down device and the P-channel as the pull-up on the high-side rail; the inherent complementary pairing eliminates the need for external resistor networks. The 20 V VDS rating provides generous headroom for both logic domains and tolerant of 5 V tolerant lines. Performance consideration: total propagation delay is dominated by the RC load on the high side. The P-channel RDS(on) of approximately 5 Ω at VGS = -2.5 V allows propagation delays in the low nanosecond range for capacitive loads below 30 pF. For higher-speed buses, parallel the SI1553DL pair with the SI1551DL dual-N configuration as an alternative.
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Battery Protection and Reverse Polarity Blocking
In single-cell Li-ion and Li-polymer battery designs, the SI1553DL-T1-E3 P-channel MOSFET functions as a high-side reverse-polarity blocker when the cell is reversed. The P-channel's -8 V VGS rating provides protection against voltage transients up to the breakdown limit, and the 410 mA continuous current is adequate for low-power IoT nodes, BLE beacons, and e-paper displays. The 0.9 V typical threshold keeps turn-on losses low when the battery is at 3.0 V minimum. Performance consideration: total forward drop at 200 mA load is approximately 1 V across the P-channel, which designers must budget into the system load line. Compared to a Schottky diode solution, the SI1553DL-T1-E3 drops about 0.2 V instead of 0.3-0.4 V, extending battery runtime by 5-10 percent in continuous-draw applications such as wireless sensor nodes.
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LED Driver Switch (PWM Dimming)
PWM dimming at audio and visual frequencies (typically 100 Hz to 1 kHz) is a key application for the SI1553DL-T1-E3 N-channel MOSFET in LED driver designs. The low 5 Ω RDS(on) at 2.5 V VGS ensures that dimming transients do not create visible flicker, and the fast turn-on/off characteristics support PWM frequencies up to several hundred kHz for high-end display backlights. The P-channel side can be used for high-side enable/disable control of the LED string itself. Performance consideration: total switching losses at 1 kHz PWM with 100 mA load are dominated by the gate charge of approximately 1.5 nC, dissipating roughly 1.5 µW average - negligible compared to the LED forward drop. Place a 100 Ω resistor in series with the gate to limit ringing and EMI on long gate traces.
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Analog Switch and Signal Multiplexing
The complementary pair in the SI1553DL-T1-E3 can be configured as a CMOS transmission gate for low-level analog signals up to ±10 V peak-to-peak. The 20 V VDS rating exceeds typical analog signal ranges, and the matched N/P on-resistance minimizes harmonic distortion in audio and instrumentation paths. This makes the device suitable for low-cost audio switching, test equipment multiplexing, and small-signal instrumentation routing. Performance consideration: total channel-to-channel leakage is in the nanoampere range, dominated by the off-state drain current at 20 V. For audio applications, the THD contribution is well below 0.01 percent at signal levels under 1 Vrms. Compared to a discrete CD4066 analog switch, the SI1553DL-T1-E3 has lower on-resistance and a smaller SC-70-6 footprint.
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IoT and Wearable Sensor Power Gating
The SI1553DL-T1-E3 is widely used in IoT and wearable designs to gate power to dormant sensors (accelerometers, gyros, heart-rate monitors) when the host MCU is in deep-sleep. The 660 mA N-channel current is more than sufficient for any single-sensor power rail, while the P-channel can be used for reverse-battery protection. The 0.9 V gate threshold allows direct drive from a 1.8 V GPIO, eliminating level shifters in low-voltage designs. Performance consideration: total quiescent leakage in the off state is dominated by the gate leakage of approximately 100 nA at 1.8 V VGS, which is critical for multi-year battery life calculations. Compared to discrete SOT-23 MOSFET pairs, the SI1553DL-T1-E3 reduces PCB area by approximately 60 percent and removes two BOM line items from the assembly.
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추천 제품 요약
엔지니어링 참조 데이터: SI1553DL-T1-E3 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | SI1553DL-T1-GE3 | SI1555DL-T1-E3 | SI1563DH-T1-E3 | SI1563EDH-T1-E3 | SI1551DL-T1-E3 |
|---|---|---|---|---|---|---|
| Brand | Vishay Intertechnology | Vishay Intertechnology | Vishay Intertechnology | Vishay Intertechnology | Vishay Intertechnology | Vishay Intertechnology |
| Package | SC-70-6 (SOT-363) | SC-70-6 (SOT-363) - same | SC-70-6 (SOT-363) - same | SC-70-6 (SOT-363) - same | SC-70-6 (SOT-363) - same | SC-70-6 (SOT-363) - same |
| Configuration | N + P complementary | N + P complementary | N + P complementary | N + P complementary | N + P complementary | Dual N-channel only |
| Halogen-Free | No (E3 is lead-free only) | Yes (GE3 suffix) | No | No | No | No |
주요 차별점
- True complementary N/P pair in SC-70-6 - eliminates need for two discrete MOSFETs (vs SI1551DL-T1-E3)
- 2.5 V gate drive optimized for direct MCU GPIO interface (vs SI1563DH-T1-E3)
- Halogen-free GE3 variant available in same footprint (vs SI1553DL-T1-GE3)
설계 노트
Estimated: at ID = 500 mA and RDS(on) = 5 Ω, the SI1553DL-T1-E3 N-channel dissipates approximately 1.25 W of heat, exceeding the 270 mW datasheet rating for the SC-70-6 package. The datasheet thermal resistance theta_JA of approximately 500 °C/W (for SC-70-6 on a standard 1 oz copper JEDEC test board) yields a junction temperature rise of over 600 °C at this load. For continuous operation above 100 mA, either reduce RDS(on) by paralleling two SI1553 N-channels, switch to the SI1555DL-T1-E3 or SI1563DH-T1-E3 in the same footprint, or add a substantial copper pour as heatsink.
Place the gate drive resistor (10 Ω to 100 Ω) as close to the SI1553DL-T1-E3 gate pin as possible to suppress ringing and limit peak gate current during fast edges. For switching frequencies above 100 kHz, add a 100 kΩ gate-source pull-down resistor on the N-channel gate to prevent false turn-on from drain-to-gate capacitance coupling during high dV/dt events. Keep source traces short and wide (≥0.5 mm) to minimize voltage drop and source-degenerative feedback.
Do not exceed the ±8 V VGS rating of the SI1553DL-T1-E3; in 5 V systems with inductive loads, add a gate protection zener or transient suppressor. The SC-70-6 (SOT-363) package is physically small - the leads are easily bent during hand prototyping. For prototypes, use a SC-70-6 to DIP adapter board. Always verify the lot traceability marking per the Vishay datasheet before assembly, as counterfeit SC-70-6 MOSFETs are common in the secondary market.
규정 준수 정보
RoHS compliant per Directive 2002/95/EC. Halogen-free variant available as SI1553DL-T1-GE3. E3 suffix confirms lead-free termination. AEC-Q100 qualification not applicable for standard consumer/industrial grade - not automotive qualified.
