SSM3K35CT - 20V N-Channel MOSFET, 0.18A, SOT-883 | Toshiba
부품 번호: SSM3K35CT ✓ 활성| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $0.42 | $0.42 |
| 10 | $0.36 | $3.60 |
| 100 | $0.27 | $27.00 |
| 500 | $0.22 | $110.00 |
| 1,000 | $0.18 | $180.00 |
| 3,000 | $0.15 | $450.00 |
SSM3K35CT 개요
A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled three-terminal device in which the gate electric field modulates the conducting channel between drain and source. Small-signal N-channel MOSFETs such as the SSM3K35CT sit in the discrete-semiconductor hierarchy: MOSFET -> field-effect transistor -> transistor -> semiconductor -> discrete component. They are typically used as low-side switches, level shifters, or analog signal gates in portable, wearable, and space-constrained designs.
Key features of the SSM3K35CT include a 20 V drain-source breakdown voltage suitable for 3.3 V and 5 V logic rails, a low gate threshold tailored to logic-level drive, a typical on-resistance of 3.0 Ω at VGS = 4 V, and a 100 mW power dissipation rating. Its CST3 (SOT-883) leadless package measures approximately 1.0 x 0.6 x 0.5 mm, making it one of the smallest standard MOSFET outlines available from Toshiba. The device is built on a silicon N-channel MOS process and is qualified for high-speed switching, supporting fast rise and fall times at low gate charge.
The device's 3.0 Ω Rds(on) at 4 V VGS yields modest conduction loss at sub-100 mA loads. Designers should note that the rated continuous drain current of 0.18 A applies to a specific reference footprint and copper area; in dense layouts with limited copper, the effective continuous current will be lower due to thermal derating. The enhancement-mode behavior means the device is off at VGS = 0 and turns on only when the gate exceeds the threshold voltage, making it directly compatible with logic-level GPIO drive.
Typical applications include load switching in smartphones and wearables, analog-signal gating in audio or sensor front ends, level translation between low-voltage microcontrollers and 5 V peripherals, high-side or low-side switching in battery-powered IoT nodes, and DC-DC converter synchronous-rectifier stages in compact point-of-load designs. Designers typically pair the SSM3K35CT with a small-signal gate resistor (typically 100 Ω to 1 kΩ) to control ringing.
When designing with this part, account for the SOT-883 land-pattern requirements: the package has no leads but exposes the drain and source through bottom-side contacts, requiring precise PCB stencil and reflow control. Confirm the thermal pad is properly soldered to maintain the rated power dissipation. Designers should consult the Toshiba datasheet for absolute maximum ratings, switching loss curves, and safe operating area before finalizing the BOM.
드롭인 대체품: SSM3K35CT — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: SSM3K35CT (동일 폼 팩터 및 풋프린트) — 차이점: Lead-Free, Package.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
SSM3K35CTC,L3F
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SSM3K35CT,L3F
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SSM3K35CTC
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SSM3K35CT
✅ 드롭인✓ 재고 있음
$0.15 / 개
데이터시트 보기 →SSM3K35CT(T5L,T
✅ 드롭인📋 참조 대체품 (카탈로그에 없음)
SSM3K35CT 최대 정격 & 전기적 특성
| Polarity | N-Channel |
| MOSFET Mode | Enhancement |
| Drain-Source Breakdown Voltage (V(BR)DSS) | 20 V |
| Continuous Drain Current (ID) | 0.18 A |
| Drain-Source On-Resistance (RDS(on)) | 3.0 Ω at VGS = 4 V |
| Power Dissipation (PD) | 100 mW (Ta) |
| 패키지 | SOT-883 (CST3), 3-pin leadless |
| Package Outline Code | CST3 (Toshiba internal), 2-1J1B |
| 실장 유형 | Surface Mount |
| Application Category | High-Speed Switching / Analog Switches |
| RoHS 상태 | Compliant |
| Lead-Free | Yes |
SSM3K35CT 핀 구성
| 핀 1 | Gate — MOSFET gate input; drive >Vth to turn on the channel |
| 핀 2 | Source — MOSFET source terminal; connected to lower-potential side of load |
| 핀 3 | Drain — MOSFET drain terminal; also serves as bottom thermal pad connected to PCB copper |
일반적인 애플리케이션
SSM3K35CT 적합 용도: 6 애플리케이션s: Wearable Load Switch, Smartphone Camera Module Interface, IoT Sensor Node Power Gating, Hearing Aid Audio Switch, Point-of-Load DC-DC Synchronous Rectifier, Level Translator / Logic Shifter.
Wearable Load Switch
The SSM3K35CT's CST3 (SOT-883) package measures approximately 1.0 x 0.6 mm, making it ideal as a low-side load switch in wearables such as fitness bands, smart watches, and Bluetooth earbuds. With V(BR)DSS = 20 V it safely switches 3.7 V Li-ion rails, and its 3.0 Ω Rds(on) at VGS = 4 V yields roughly 90 mV drop at 30 mA typical quiescent loads. Driven directly from a microcontroller GPIO at 3.3 V, the enhancement-mode N-channel design eliminates the need for a charge pump. The 100 mW power dissipation rating supports the brief inrush currents required by LED drivers and sensor ICs.
추천
Smartphone Camera Module Interface
Inside a smartphone camera module the SSM3K35CT serves as a high-speed analog switch that gates MIPI or parallel image-sensor data lines during power-down or sensor-mode transitions. The 20 V V(BR)DSS gives substantial margin against ESD events, while the enhancement-mode behavior guarantees the signal path is fully isolated when the gate is at logic low. With 3.0 Ω Rds(on) the device adds negligible insertion loss on 100 Ω differential pairs. The SOT-883 outline occupies under 0.6 mm² of board area, fitting easily between the image sensor and the ISP.
추천
IoT Sensor Node Power Gating
Battery-powered IoT sensor nodes rely on the SSM3K35CT to gate power to downstream subsystems such as gas sensors, accelerometers, and RF transceivers during deep-sleep states. The 20 V drain-source rating accommodates 4.2 V Li-ion peaks and inductive transients from relay-driven actuators. At 3.0 Ω Rds(on) with VGS = 4 V, the SSM3K35CT adds only 60 mV of drop at 20 mA, preserving battery runtime. Its sub-microamp off-state leakage prevents parasitic drain on coin-cell or Li-Po batteries during months-long standby.
추천
Hearing Aid Audio Switch
In behind-the-ear and in-canal hearing aids the SSM3K35CT functions as a low-leakage analog switch for microphone and receiver paths, supporting program-changeover between omni-directional and directional modes. The 1.0 x 0.6 mm SOT-883 footprint fits on flex PCBs inside a 5 mm-diameter shell. Its enhancement-mode N-channel topology ensures clean audio signal paths with minimal harmonic distortion, while the 3.0 Ω Rds(on) provides a flat 20 kHz audio response. The 20 V breakdown protects against ESD events from skin contact during insertion.
추천
Point-of-Load DC-DC Synchronous Rectifier
Within compact point-of-load buck converters in FPGA and ASIC power trees, the SSM3K35CT can serve as a synchronous rectifier on the low-side switch position when the load current stays below 180 mA. The 3.0 Ω Rds(on) at VGS = 4 V produces 100-200 mV of switch-node ripple at 50 mA, manageable for sub-watt rails. The 20 V V(BR)DSS safely handles 5 V and 12 V intermediate bus voltages. The SOT-883 outline keeps the high-frequency loop area minimal, reducing EMI and parasitic inductance.
추천
Level Translator / Logic Shifter
The SSM3K35CT enables discrete bidirectional level translation between 1.8 V, 3.3 V, and 5 V logic domains in mixed-voltage I2C, SPI, and UART buses. Wired as an N-channel pass-FET with gate tied to the higher-voltage rail, the 3.0 Ω Rds(on) introduces minimal signal attenuation at low data rates. Its 20 V V(BR)DSS protects against inadvertent shorts to higher-voltage rails, while the SOT-883 package fits between the level-shifting pads of micro header connectors. Compared to dedicated level-shifter ICs, this topology saves cost and board area.
추천
추천 제품 요약
엔지니어링 참조 데이터: SSM3K35CT — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | SSM3K35CTC,L3F | SSM3K35CT,L3F | SSM3K35CTC | SSM3K35CT | SSM3K35CT(T5L,T |
|---|---|---|---|---|---|---|
| Brand | Toshiba | Toshiba | Toshiba | Toshiba | Toshiba | Toshiba |
| Package | CST3 (SOT-883) | CST3C (SOT-883) | CST3 (SOT-883) | CST3C (SOT-883) | CST3 (SOT-883) | CST3 (SOT-883) |
| Polarity | N-Channel | N-Channel | N-Channel | N-Channel | N-Channel | N-Channel |
| V(BR)DSS | 20 V | 20 V | 20 V | 20 V | 20 V | 20 V |
| Continuous Drain Current | 0.18 A | 0.25 A | 0.18 A | 0.25 A | 0.18 A | 0.18 A |
| Rds(on) at VGS = 4 V | 3.0 Ω | 1.1 Ω at VGS = 4.5 V | 3.0 Ω | 1.1 Ω at VGS = 4.5 V | 3.0 Ω | 3.0 Ω |
| Power Dissipation | 100 mW | 500 mW | 100 mW | 500 mW | 100 mW | 100 mW |
| Operating Mode | Enhancement | Enhancement | Enhancement | Enhancement | Enhancement | Enhancement |
주요 차별점
- Smaller footprint than SOT-23 alternatives (vs BSS84 (SOT-23 P-channel))
- Logic-level direct drive from 3.3 V GPIO (vs Standard-threshold MOSFETs requiring VGS = 10 V)
- Same package as higher-current upgrade (vs SSM3K35CTC (CST3C))
설계 노트
The SSM3K35CT's CST3 (SOT-883) package has no gull-wing leads; drain and source are connected via bottom-side metallization pads. Estimated: with a 0.6 mm x 0.3 mm pad layout, maintain 0.2 mm solder mask expansion and use NSMD pads to ensure reliable solder joint formation. The drain pad also serves as the primary thermal path - design a copper pour of at least 2 mm² under the device to meet the 100 mW power dissipation rating at 25 °C ambient.
Driving VGS below the threshold will leave the SSM3K35CT in its off state; confirm microcontroller GPIO high-level output voltage exceeds the typical Vth of the device under all temperature corners. Estimated: if Vth max is 1.5 V at -40 °C, a 3.3 V GPIO provides 1.8 V of margin which is sufficient. Avoid using the SSM3K35CT in circuits where the gate could float - always tie the gate to a defined logic level through a pull-down or pull-up resistor to prevent partial turn-on and unwanted current flow.
The 100 mW power dissipation rating applies at 25 °C ambient on Toshiba's reference PCB. Estimated: at 0.18 A continuous current with 3.0 Ω Rds(on), conduction loss reaches 97 mW - already at the thermal limit. In real-world layouts with smaller copper pours, junction temperature may rise above 100 °C. For sustained high-load operation, derate to 100 mA or smaller, or upgrade to the SSM3K35CTC which supports 500 mW dissipation with a larger thermal pad.
When using the SSM3K35CT as an analog switch in audio or data paths, add a 100 Ω to 1 kΩ gate resistor to dampen LC ringing caused by the gate capacitance and source inductance. Estimated: gate charge Qg of approximately 0.5 nC combined with a 1 kΩ resistor yields a 50 ns gate rise time, reducing high-frequency EMI. For high-speed switching above 1 MHz, keep the gate-drive loop compact and place a small ferrite bead in series with the source to suppress ringing on the switch node.
규정 준수 정보
RoHS compliance per Toshiba product page; AEC-Q100 qualification not listed. REACH, halogen-free, and conflict-minerals status not explicitly stated in verified data.
