EP1810JC-25 vs EP1810JC-35 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810JC-25 disebabkan oleh Intel dan EP1810JC-35 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP1810JC-25 EP1810JC-35
Merek Intel Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Obsolete
Product Type Classic EPLD (Erasable Programmable Logic Device) —
Family Altera/Intel Classic EPLD (EP1810 series) —
Macrocells 48 —
Propagation Delay (tPD) 25 ns —
Maximum Toggle Frequency [DATA_NEEDED: max fMAX] —
Input Lines 60 (including I/O) —
I/O Lines 48 —
Dedicated Inputs 12 —
External Clock Inputs 4 —
Supply Voltage (VCC) 4.75 V to 5.25 V —
Suhu Operasi -40 °C to 85 °C (industrial, per distributor listings) —
Technology CMOS, UV-erasable (windowed ceramic DIP) —
Kemasan 28-pin ceramic DIP (J) with quartz window —
Jenis Pemasangan Through-hole Surface Mount (J-Lead)
Erasure Method UV light (windowed package) UV (quartz-windowed ceramic package)
Status RoHS [DATA_NEEDED: RoHS compliance status] Compliant (per Altera listing)
Status Lingkungan Hidup NRND (Not Recommended for New Designs) —
Device Family — Classic EPLD (EP1810)
Device Type — UV-Erasable Complex PLD (UV PLD / CPLD)
Number of Macrocells — 48
Propagation Delay (tpd) — 35 ns (max)
Frekuensi Klock Maksimum — [DATA_NEEDED: fmax for this speed grade]
Process Technology — CMOS
Supply Voltage (Vcc) — 5 V (nominal)
Maximum Supply Voltage — 5.25 V (per distributor listing)
Package Type — CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ)
Number of Terminals — 68
Terminal Form — J-Bend
Gambaran Suhu Operasi — 0°C to 70°C (Commercial)
Temperature Grade — Commercial
Lead-Free Status — Lead-free (per distributor listing)
Logic Architecture — Programmable AND/OR array with macrocell outputs

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