EP1810JC-25 vs EP1810JC-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JC-25 sa pamamagitan ng Intel at EP1810JC-35 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810JC-25 EP1810JC-35
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Product Type Classic EPLD (Erasable Programmable Logic Device) —
Family Altera/Intel Classic EPLD (EP1810 series) —
Macrocells 48 —
Propagation Delay (tPD) 25 ns —
Maximum Toggle Frequency [DATA_NEEDED: max fMAX] —
Input Lines 60 (including I/O) —
I/O Lines 48 —
Dedicated Inputs 12 —
External Clock Inputs 4 —
Supply Voltage (VCC) 4.75 V to 5.25 V —
Temperature na Operasyon -40 °C to 85 °C (industrial, per distributor listings) —
Technology CMOS, UV-erasable (windowed ceramic DIP) —
Packhaging 28-pin ceramic DIP (J) with quartz window —
Uri ng Pagpapasok Through-hole Surface Mount (J-Lead)
Erasure Method UV light (windowed package) UV (quartz-windowed ceramic package)
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] Compliant (per Altera listing)
Katayuan ng Lifecycle NRND (Not Recommended for New Designs) —
Device Family — Classic EPLD (EP1810)
Device Type — UV-Erasable Complex PLD (UV PLD / CPLD)
Number of Macrocells — 48
Propagation Delay (tpd) — 35 ns (max)
Maksimum na Taktiko ng Oras — [DATA_NEEDED: fmax for this speed grade]
Process Technology — CMOS
Supply Voltage (Vcc) — 5 V (nominal)
Maximum Supply Voltage — 5.25 V (per distributor listing)
Package Type — CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ)
Number of Terminals — 68
Terminal Form — J-Bend
Hanay ng Temperature na Operasyon — 0°C to 70°C (Commercial)
Temperature Grade — Commercial
Lead-Free Status — Lead-free (per distributor listing)
Logic Architecture — Programmable AND/OR array with macrocell outputs

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