EP1810JC-25 vs EP1810JC35 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810JC-25 disebabkan oleh Intel dan EP1810JC35 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EP1810JC-25 | EP1810JC35 |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | UV-erasable / OTP Complex PLD (EPLD) |
| Family | Altera/Intel Classic EPLD (EP1810 series) | Altera Classic EPLD |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 25 ns | 35 ns |
| Maximum Toggle Frequency | [DATA_NEEDED: max fMAX] | — |
| Input Lines | 60 (including I/O) | — |
| I/O Lines | 48 | — |
| Dedicated Inputs | 12 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Suhu Operasi | -40 °C to 85 °C (industrial, per distributor listings) | 0 C to +70 C (Commercial) |
| Technology | CMOS, UV-erasable (windowed ceramic DIP) | — |
| Kemasan | 28-pin ceramic DIP (J) with quartz window | PLCC-68 (J-lead, ceramic) |
| Jenis Pemasangan | Through-hole | — |
| Erasure Method | UV light (windowed package) | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance for EP1810JC35] |
| Status Lingkungan Hidup | NRND (Not Recommended for New Designs) | — |
| Logic Gates (typ.) | — | [DATA_NEEDED: logic gates count] |
| Maximum User I/O Pins | — | [DATA_NEEDED: user I/O count for PLCC-68] |
| Frekuensi Klock Maksimum | — | 40 MHz |
| Supply Voltage (VCC max) | — | 5.25 V |
| Supply Voltage (VCC min) | — | [DATA_NEEDED: VCC minimum] |
| Process Technology | — | CMOS EPROM cell |
| Package Code | — | QCCJ |
| Terminal Form | — | J-BEND |
| Number of Terminals | — | 68 |
| Programming | — | UV-erase (windowed) or OTP |
| Development Tool | — | Altera MAX+plus II / A+plus |