EP1810JC-25 vs EP1810JC35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JC-25 sa pamamagitan ng Intel at EP1810JC35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810JC-25 EP1810JC35
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Product Type Classic EPLD (Erasable Programmable Logic Device) UV-erasable / OTP Complex PLD (EPLD)
Family Altera/Intel Classic EPLD (EP1810 series) Altera Classic EPLD
Macrocells 48 48
Propagation Delay (tPD) 25 ns 35 ns
Maximum Toggle Frequency [DATA_NEEDED: max fMAX] —
Input Lines 60 (including I/O) —
I/O Lines 48 —
Dedicated Inputs 12 —
External Clock Inputs 4 —
Supply Voltage (VCC) 4.75 V to 5.25 V —
Temperature na Operasyon -40 °C to 85 °C (industrial, per distributor listings) 0 C to +70 C (Commercial)
Technology CMOS, UV-erasable (windowed ceramic DIP) —
Packhaging 28-pin ceramic DIP (J) with quartz window PLCC-68 (J-lead, ceramic)
Uri ng Pagpapasok Through-hole —
Erasure Method UV light (windowed package) —
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance for EP1810JC35]
Katayuan ng Lifecycle NRND (Not Recommended for New Designs) —
Logic Gates (typ.) — [DATA_NEEDED: logic gates count]
Maximum User I/O Pins — [DATA_NEEDED: user I/O count for PLCC-68]
Maksimum na Taktiko ng Oras — 40 MHz
Supply Voltage (VCC max) — 5.25 V
Supply Voltage (VCC min) — [DATA_NEEDED: VCC minimum]
Process Technology — CMOS EPROM cell
Package Code — QCCJ
Terminal Form — J-BEND
Number of Terminals — 68
Programming — UV-erase (windowed) or OTP
Development Tool — Altera MAX+plus II / A+plus

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