EP1810JC-25 vs EP1810JC35 比較
詳細並排比較 EP1810JC-25 由 Intel 與 EP1810JC35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810JC-25 | EP1810JC35 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | UV-erasable / OTP Complex PLD (EPLD) |
| Family | Altera/Intel Classic EPLD (EP1810 series) | Altera Classic EPLD |
| Macrocells | 48 | 48 |
| Propagation Delay (tPD) | 25 ns | 35 ns |
| Maximum Toggle Frequency | [DATA_NEEDED: max fMAX] | — |
| Input Lines | 60 (including I/O) | — |
| I/O Lines | 48 | — |
| Dedicated Inputs | 12 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| 工作溫度 | -40 °C to 85 °C (industrial, per distributor listings) | 0 C to +70 C (Commercial) |
| Technology | CMOS, UV-erasable (windowed ceramic DIP) | — |
| 封裝 | 28-pin ceramic DIP (J) with quartz window | PLCC-68 (J-lead, ceramic) |
| 安裝類型 | Through-hole | — |
| Erasure Method | UV light (windowed package) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance for EP1810JC35] |
| 生命週期狀態 | NRND (Not Recommended for New Designs) | — |
| Logic Gates (typ.) | — | [DATA_NEEDED: logic gates count] |
| Maximum User I/O Pins | — | [DATA_NEEDED: user I/O count for PLCC-68] |
| 最大時脈頻率 | — | 40 MHz |
| Supply Voltage (VCC max) | — | 5.25 V |
| Supply Voltage (VCC min) | — | [DATA_NEEDED: VCC minimum] |
| Process Technology | — | CMOS EPROM cell |
| Package Code | — | QCCJ |
| Terminal Form | — | J-BEND |
| Number of Terminals | — | 68 |
| Programming | — | UV-erase (windowed) or OTP |
| Development Tool | — | Altera MAX+plus II / A+plus |