EP1810LI-45 vs EP1810JC-45 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP1810LI-45 disebabkan oleh Rochester Electronics dan EP1810JC-45 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP1810LI-45 EP1810JC-45
Merek Rochester Electronics Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Aktif NRND
Product Type EPLD (Erasable Programmable Logic Device) Classic EPLD (Erasable Programmable Logic Device)
Family Altera Classic EP1810 (Classic EPLD Family)
Usable Gates 900 —
Macrocells 48 48
Maximum User I/O 64 inputs / 48 outputs —
Pin-to-Pin Logic Delay (tPD) 45 ns —
Counter Frequency (fCNT) up to 100 MHz —
Setup Time (tSU) [DATA_NEEDED: setup time] —
Technology CMOS, UV-erasable EPROM configuration CMOS, UV-erasable
Tegangan Pemberi Arus 5 V —
Gambaran Suhu Operasi -40 C to +85 C (Industrial, 'I' suffix) —
Kemasan 68-pin PLCC / PQCC68 (J-Lead) PLCC-68 (QCCJ, J-Lead, windowed ceramic)
Logic Blocks 12 LABs of 4 macrocells each —
Configuration Memory Non-volatile UV-erasable EPROM —
Programming Method Altera programming hardware with MAX+PLUS II / legacy tools —
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance not stated in verified data]
Manufacturer Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) —
Equivalent Gates — 2100 gates
Dedicated Inputs — 12
I/O Pins — 48
Total User I/O — 60
Propagation Delay (tpd) — 45 ns
Frekuensi Klock Maksimum — 33.3 MHz
Maximum Supply Voltage — 5.25 V
Kiraan Pin — 68
Package Code — QCCJ
Temperature Grade — Commercial
Jenis Pemasangan — Surface Mount

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