EP1810LI-45 vs EP1810JC-45 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LI-45 sa pamamagitan ng Rochester Electronics at EP1810JC-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810LI-45 EP1810JC-45
Brand Rochester Electronics Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo NRND
Product Type EPLD (Erasable Programmable Logic Device) Classic EPLD (Erasable Programmable Logic Device)
Family Altera Classic EP1810 (Classic EPLD Family)
Usable Gates 900 —
Macrocells 48 48
Maximum User I/O 64 inputs / 48 outputs —
Pin-to-Pin Logic Delay (tPD) 45 ns —
Counter Frequency (fCNT) up to 100 MHz —
Setup Time (tSU) [DATA_NEEDED: setup time] —
Technology CMOS, UV-erasable EPROM configuration CMOS, UV-erasable
Volte ng Pagbibigay 5 V —
Hanay ng Temperature na Operasyon -40 C to +85 C (Industrial, 'I' suffix) —
Packhaging 68-pin PLCC / PQCC68 (J-Lead) PLCC-68 (QCCJ, J-Lead, windowed ceramic)
Logic Blocks 12 LABs of 4 macrocells each —
Configuration Memory Non-volatile UV-erasable EPROM —
Programming Method Altera programming hardware with MAX+PLUS II / legacy tools —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance not stated in verified data]
Manufacturer Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) —
Equivalent Gates — 2100 gates
Dedicated Inputs — 12
I/O Pins — 48
Total User I/O — 60
Propagation Delay (tpd) — 45 ns
Maksimum na Taktiko ng Oras — 33.3 MHz
Maximum Supply Voltage — 5.25 V
Bilang ng Pin — 68
Package Code — QCCJ
Temperature Grade — Commercial
Uri ng Pagpapasok — Surface Mount

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