EP1810LI-45 vs EP1810JC-45 比較
詳細並排比較 EP1810LI-45 由 Rochester Electronics 與 EP1810JC-45 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP1810LI-45 - Classic EPLD, 900 Gates, 48 Macrocells, 45ns, PQCC68 | Rochester Electronics (Altera)
EP1810LI-45 ✓ 啟用中規格比較
| 參數 | EP1810LI-45 | EP1810JC-45 |
|---|---|---|
| 品牌 | Rochester Electronics | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | NRND |
| Product Type | EPLD (Erasable Programmable Logic Device) | Classic EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic | EP1810 (Classic EPLD Family) |
| Usable Gates | 900 | — |
| Macrocells | 48 | 48 |
| Maximum User I/O | 64 inputs / 48 outputs | — |
| Pin-to-Pin Logic Delay (tPD) | 45 ns | — |
| Counter Frequency (fCNT) | up to 100 MHz | — |
| Setup Time (tSU) | [DATA_NEEDED: setup time] | — |
| Technology | CMOS, UV-erasable EPROM configuration | CMOS, UV-erasable |
| 供應電壓 | 5 V | — |
| 工作溫度範圍 | -40 C to +85 C (Industrial, 'I' suffix) | — |
| 封裝 | 68-pin PLCC / PQCC68 (J-Lead) | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Logic Blocks | 12 LABs of 4 macrocells each | — |
| Configuration Memory | Non-volatile UV-erasable EPROM | — |
| Programming Method | Altera programming hardware with MAX+PLUS II / legacy tools | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| Manufacturer | Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) | — |
| Equivalent Gates | — | 2100 gates |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Propagation Delay (tpd) | — | 45 ns |
| 最大時脈頻率 | — | 33.3 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| 腳位數 | — | 68 |
| Package Code | — | QCCJ |
| Temperature Grade | — | Commercial |
| 安裝類型 | — | Surface Mount |