EP610IDC-10 vs EP610IDC-15 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP610IDC-10 disebabkan oleh Intel dan EP610IDC-15 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Intel
EP610IDC-15 EP610IDC-15 - 16-Macrocell Classic EPLD, 15ns, 24-CerDIP | Intel

EP610IDC-15 - 16-Macrocell Classic EPLD, 15ns, 24-CerDIP | Intel

EP610IDC-15 ⚠ Bahagian terakhir untuk beli

Pengandingan Spesifikasi

Parametr EP610IDC-10 EP610IDC-15
Merek Intel Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Masa Terakhir Dibeli
Device Family Altera Classic EPLD Altera Classic EPLD
Logic Capacity 300 usable gates —
Macrocell Count 16 macrocells —
Pin-to-Pin Logic Delay (tpd) 10 ns —
Maximum Counter Frequency (fCNT) 100 MHz —
Supply Voltage (VCC) 5 V (nominal) 4.75 V to 5.25 V (5 V nominal)
I/O Logic Compatibility 100% TTL emulation —
Technology CMOS, UV-erasable (windowed ceramic) —
Package Type 24-pin Ceramic DIP (CDIP) —
Dedicated Inputs 4 —
I/O Pins 20 24 (per package; macrocell-programmable)
Gambaran Suhu Operasi 0 °C to +70 °C (commercial) —
Programmable Interconnect Yes (on-chip) —
In-System Programmability Yes (via MAX+PLUS II) —
Boundary-Scan Test Yes (per device documentation) —
Status RoHS [DATA_NEEDED: RoHS status of CDIP-10 variant] [DATA_NEEDED: RoHS status of CerDIP variant]
Jenis Pemasangan Through-hole Through-hole
Macrocells — 16
Usable Gates — 300
Propagation Delay (tPD) — 15 ns
Maximum Frequency — 66 MHz
Suhu Operasi — 0C to +70C (commercial)
Process Technology — CMOS, UV-erasable / OTP
Kemasan — 24-pin CerDIP (ceramic DIP)
Logic-Block Architecture — AND/OR macrocell array with programmable flip-flops
Program/Erase — UV-erasable, OTP-compatible
Development Tool — MAX+PLUS II
Programming Current — 11.0 mA typical (per Classic family datasheet)

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