EP610IDC-10 vs EP610IDC-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610IDC-10 sa pamamagitan ng Intel at EP610IDC-15 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP610IDC-10 EP610IDC-15
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Device Family Altera Classic EPLD Altera Classic EPLD
Logic Capacity 300 usable gates —
Macrocell Count 16 macrocells —
Pin-to-Pin Logic Delay (tpd) 10 ns —
Maximum Counter Frequency (fCNT) 100 MHz —
Supply Voltage (VCC) 5 V (nominal) 4.75 V to 5.25 V (5 V nominal)
I/O Logic Compatibility 100% TTL emulation —
Technology CMOS, UV-erasable (windowed ceramic) —
Package Type 24-pin Ceramic DIP (CDIP) —
Dedicated Inputs 4 —
I/O Pins 20 24 (per package; macrocell-programmable)
Hanay ng Temperature na Operasyon 0 °C to +70 °C (commercial) —
Programmable Interconnect Yes (on-chip) —
In-System Programmability Yes (via MAX+PLUS II) —
Boundary-Scan Test Yes (per device documentation) —
Tindminan RoHS [DATA_NEEDED: RoHS status of CDIP-10 variant] [DATA_NEEDED: RoHS status of CerDIP variant]
Uri ng Pagpapasok Through-hole Through-hole
Macrocells — 16
Usable Gates — 300
Propagation Delay (tPD) — 15 ns
Maximum Frequency — 66 MHz
Temperature na Operasyon — 0C to +70C (commercial)
Process Technology — CMOS, UV-erasable / OTP
Packhaging — 24-pin CerDIP (ceramic DIP)
Logic-Block Architecture — AND/OR macrocell array with programmable flip-flops
Program/Erase — UV-erasable, OTP-compatible
Development Tool — MAX+PLUS II
Programming Current — 11.0 mA typical (per Classic family datasheet)

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