EP910DI-35 vs EP910DC-35 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EP910DI-35 disebabkan oleh Altera dan EP910DC-35 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EP910DI-35 EP910DC-35
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Aktif Obsolete
Product Type EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EPLD Classic EPLD EP910
Macrocells 24 24
Usable Gates 450 900 gates
Propagation Delay (tPD) 35 ns —
Maximum Toggle Frequency (fCNT) 28.6 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
Supply Current (ICC) 40 mA typical —
Dedicated Inputs 10 12
Bidirectional I/O Pins 20 —
Total Pins 40 —
Kemasan CDIP-40 (Ceramic DIP with UV window) 40-pin CDIP (Ceramic DIP) with quartz window
Jenis Pemasangan Through-Hole —
Suhu Operasi -40C to +85C (industrial) 0 °C to +70 °C (commercial)
Technology CMOS, UV-erasable EPROM CMOS, UV-erasable EPROM cell
Programming Method EPROM programmer + JEDEC fuse map JEDEC fuse map via device programmer; UV erase
Erasure Method UV light through quartz window —
Status RoHS [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Logic Family PAL-type AND/OR array with D flip-flops —
Manufacturer Original Altera; long-term authorized by Rochester Electronics, LLC —
Device Type — UV-Erasable CMOS PLD (PAL-type)
Architecture — PAL-type sum-of-products AND-OR array
Product Terms — 240
I/O Pins — 24
Total Inputs — 36
Propagation Delay (tpd) — 35 ns
Frekuensi Klock Maksimum — 37 MHz (typical, internal)
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
Lead Pitch — 2.540 mm
Termination Style — Through-Hole
Lifecycle — Obsolete / last-time-buy from authorized distributors

Laporan Datasheet & Sumber

Lihat Semua Produk Buat BOQ Minta Bao Harga