EP910DI-35 vs EP910DC-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910DI-35 sa pamamagitan ng Altera at EP910DC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910DI-35 | EP910DC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Classic EPLD EP910 |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | 900 gates |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Toggle Frequency (fCNT) | 28.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Supply Current (ICC) | 40 mA typical | — |
| Dedicated Inputs | 10 | 12 |
| Bidirectional I/O Pins | 20 | — |
| Total Pins | 40 | — |
| Packhaging | CDIP-40 (Ceramic DIP with UV window) | 40-pin CDIP (Ceramic DIP) with quartz window |
| Uri ng Pagpapasok | Through-Hole | — |
| Temperature na Operasyon | -40C to +85C (industrial) | 0 °C to +70 °C (commercial) |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM cell |
| Programming Method | EPROM programmer + JEDEC fuse map | JEDEC fuse map via device programmer; UV erase |
| Erasure Method | UV light through quartz window | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Logic Family | PAL-type AND/OR array with D flip-flops | — |
| Manufacturer | Original Altera; long-term authorized by Rochester Electronics, LLC | — |
| Device Type | — | UV-Erasable CMOS PLD (PAL-type) |
| Architecture | — | PAL-type sum-of-products AND-OR array |
| Product Terms | — | 240 |
| I/O Pins | — | 24 |
| Total Inputs | — | 36 |
| Propagation Delay (tpd) | — | 35 ns |
| Maksimum na Taktiko ng Oras | — | 37 MHz (typical, internal) |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V nominal) |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |
| Lifecycle | — | Obsolete / last-time-buy from authorized distributors |