10AX090N2F40I1SG - Arria 10 GX FPGA, 900K LE, 1517-FCBGA | Intel
MPN: 10AX090N2F40I1SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4250 | $4,250.00 |
| 10 | $3950 | $39,500.00 |
| 100 | $3520 | $352,000.00 |
| 500 | $3210 | $1,605,000.00 |
| 1,000 | $2985 | $2,985,000.00 |
10AX090N2F40I1SG Overview
An FPGA (Field-Programmable Gate Array) is a semiconductor device containing an array of configurable logic blocks (CLBs), programmable interconnect, and dedicated hard IP such as transceivers, DSP blocks, and embedded memory. FPGAs sit within the broader hierarchy of programmable logic devices (PLDs), parallel to CPLDs (less complex, non-volatile) and ASICs (factory-programmed, lower per-unit cost at volume). FPGAs are used when design flexibility, time-to-market, or algorithm parallelism outweigh the cost premium of custom silicon.
Key features of the 10AX090N2F40I1SG include 600 high-speed user I/O supporting LVDS, LVCMOS, and memory-interface standards, 24 transceivers rated up to 17.4 Gbps for protocols such as PCIe Gen3 x8 and 10GbE/40GbE, and a 1.5 GHz ARM Cortex-A9 hard processor subsystem for SoC integration. The device supports up to 28.05 Gbps chip-to-chip interconnects through hardened HSSI channels and includes 1,518 embedded 18x19 multipliers for DSP workloads in radio, beamforming, and signal processing pipelines.
The Arria 10 GX architecture separates logic fabric from a rich hard-IP periphery, allowing deterministic timing closure at clock rates of several hundred MHz per logic block. The 20 nm process node enables a balance between static and dynamic power, with Intel's Smart Voltage ID (SmartVID) providing per-die voltage scaling from approximately 0.85 V to 0.95 V at the core.
Typical applications for the 10AX090N2F40I1SG include 100G/40G line-card MAC and framer logic, ASIC prototyping in mid-range wireless baseband, military radar and SIGINT front-end digitizers, medical imaging reconstruction pipelines, and broadcast video processing engines. The -I1 industrial speed grade supports operation across -40C to +100C ambient, suiting outdoor and ruggedized deployments.
When designing with the 1517-ball FCBGA, pay close attention to PCB stackup and via-in-pad geometry - the 1.0 mm ball pitch demands laser-drilled microvias or sequential lamination. The transceiver channels require matched-length routing with controlled differential impedance, and the FPGA's SmartVID supply must be fed from a PMBus-compliant regulator such as the Intel EM2K12008.
This page synthesizes distributor pricing across DigiKey, Mouser, and Octopart, plus cross-references to same-package Arria 10 GX variants and engineering design notes not consolidated in the manufacturer datasheet.
Drop-in alternatives for 10AX090N2F40I1SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with 10AX090N2F40I1SG (same form factor and footprint) — differing in Package, Process Technology, DSP Blocks, Hard Memory Controllers, Transceivers.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AX090N2F40I2SG
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$6185 / Unit
View Datasheet →10AX090N3F40I1SG
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
10AX090N2F40E1SG
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
10AX066N2F40I1SG
✅ Drop-In📋 Reference alternative (not in catalog)
10AX066K2F40I1SG
✅ Drop-In✓ In Stock
$3395 / Unit
View Datasheet →10AX066K1F40I1SG
✅ Drop-In✓ In Stock
$2820 / Unit
View Datasheet →10AX090N2F40I1SG Maximum Ratings & Electrical Characteristics
| Series | Arria 10 GX |
| Logic Elements | 900,000 |
| Embedded Memory Bits | 59,234,304 |
| User I/O Count | 600 |
| Package | 1517-BBGA, FCBGA |
| Ball Pitch | 1.0 mm |
| Operating Temperature | -40C to +100C (Industrial) |
| Process Node | 20 nm (TSMC) |
| Core Voltage | 0.85 V to 0.95 V (SmartVID) |
| Transceiver Data Rate | Up to 17.4 Gbps |
| Hard Processor Subsystem | Dual-core ARM Cortex-A9 MPCore |
| Embedded Multipliers | 1,518 (18x19) |
| Speed Grade | -1 |
| RoHS Status | Compliant |
| Lead-Free | Yes |
| Mounting Type | Surface Mount (BGA) |
10AX090N2F40I1SG 1517-bbga, fcbga Pin Configuration Guide
Pin configuration for 10AX090N2F40I1SG (1517-bbga, fcbga package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX090N2F40I1SG.
Refer to the datasheet for full pin configuration.
Typical Applications
10AX090N2F40I1SG is suitable for 6 applications: 100G/40G Ethernet Line-Card MAC and Framer, Wireless Baseband and Fronthaul CPRI, ASIC Prototyping and Emulation, Medical Imaging Reconstruction, Broadcast Video Processing and SDI Routing, Radar and SIGINT Signal Processing.
100G/40G Ethernet Line-Card MAC and Framer
The 10AX090N2F40I1SG's 17.4 Gbps transceivers and 900K logic elements make it an ideal single-chip MAC and framer for 100G Ethernet line cards in top-of-rack switches and carrier aggregation platforms. The 600 user I/O pins provide ample interface bandwidth to external QSFP28 optics and board-level high-speed backplanes. Designers typically map 4×25G or 10×10G PCS lanes into the FPGA's hard HSSI blocks, leaving the logic fabric free for packet classification, queue management, and OAM offload. The 59 Mbit embedded memory accommodates large packet buffers at line-rate. Power dissipation of the FPGA core plus transceivers typically runs 18-25 W, requiring substantial PCB copper and airflow.
Recommended
Wireless Baseband and Fronthaul CPRI
For LTE Advanced Pro and 5G NR fronthaul, the 10AX090N2F40I1SG implements CPRI Option 7 (10.137 Gbps) or eCPRI (10G/25G Ethernet) over its 17.4 Gbps transceivers. The 1,518 embedded 18x19 multipliers accelerate FFT/iFFT, channel estimation, and Massive MIMO beamforming weights, all within industrial -40C to +100C operation. The 900K LE budget accommodates full PHY plus MAC scheduler for small-cell deployments. Pair with external RFICs via analog JESD204B/C interfaces routed through the FPGA's high-speed LVDS pins. This design pattern is widely adopted in BBU (baseband unit) reference designs.
Recommended
ASIC Prototyping and Emulation
The 10AX090N2F40I1SG is widely deployed as a mid-range ASIC prototype target, providing 900K logic elements across multiple identical FPGAs partitioned via the Intel FPGA Prototyping flow. Industrial temperature operation supports bring-up in production-environment test racks. Designers map RTL using Quartus Prime synthesis, achieving up to 75% logic utilization after place-and-route. The 17.4 Gbps transceivers emulate multi-channel ASIC SERDES, and the 1.0 mm FCBGA enables repeatable signal integrity on standard 18-layer PCBs. Compared to ASIC emulation farms built from smaller FPGAs, a 10AX090-based farm reduces chip count and interconnect latency.
Recommended
Medical Imaging Reconstruction
CT, MRI, and PET reconstruction pipelines demand parallel arithmetic on multi-dimensional data sets - a workload well-suited to the 10AX090N2F40I1SG's 1,518 18x19 multipliers and 900K LE. The FPGA performs filtered back-projection (FBP) or iterative reconstruction in real time at 30+ frames per second for 1024x1024 CT slices. The 59 Mbit embedded memory holds large intermediate image arrays, and the 600 user I/O pins connect to LVDS-based detector ASIC arrays. Industrial temperature tolerance supports equipment-room deployment. The Arria 10 GX's deterministic timing enables reproducible medical-grade image quality required for FDA submission.
Recommended
Broadcast Video Processing and SDI Routing
The 10AX090N2F40I1SG handles SDI routing, format conversion, and HDR processing in 4K/UHD broadcast studios. Its transceivers carry 12G-SDI (11.88 Gbps) per channel, supporting up to four 4K streams simultaneously with on-FPGA deinterlacer and color-space converter blocks. The 900K LE fabric implements scalable multiviewers and production switchers. Industrial temperature operation is required for outside-broadcast truck deployments subject to ambient extremes. Reference designs from Intel PSG show complete 4K UHD SDI router implementations using this density point.
Recommended
Radar and SIGINT Signal Processing
Phased-array radar, electronic warfare, and SIGINT (signals intelligence) systems use the 10AX090N2F40I1SG for real-time digital beamforming and pulse compression. The 1,518 DSP blocks execute complex FFTs at sample rates up to 500 MSPS across 16 channels. The 17.4 Gbps transceivers carry digitized RF streams from front-end ADCs (e.g. EV10AS168A) into the FPGA. The 900K LE accommodates multi-element digital beamformers and adaptive jamming cancellers. Industrial temperature operation supports military ground-mobile and shipboard installations, where ambient temperatures regularly exceed 70C.
Recommended
Recommended Products Summary
Engineering reference data for 10AX090N2F40I1SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX090N2F40I2SG | 10AX090N3F40I1SG | 10AX090N2F40E1SG | 10AX066N2F40I1SG | 10AX066K2F40I1SG | 10AX066K1F40I1SG |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1517-BBGA, FCBGA (F40) | 1517-BBGA, FCBGA (F40) - same | 1517-BBGA, FCBGA (F40) - same | 1517-BBGA, FCBGA (F40) - same | 1517-BBGA, FCBGA (F40) - same | 1517-BBGA, FCBGA (F40) - same | 1517-BBGA, FCBGA (F40) - same |
| Logic Elements | 900,000 | 900,000 | 900,000 | 900,000 | 660,000 (-27%) | 660,000 (-27%) | 660,000 (-27%) |
| Embedded Memory | 59.2 Mbit | 59.2 Mbit | 59.2 Mbit | 59.2 Mbit | 42 Mbit | 42 Mbit | 42 Mbit |
| User I/O | 600 | 600 | 600 | 600 | 492 | 492 | 492 |
| Temperature Grade | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Commercial Extended (0C to +100C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) |
| Speed Grade | -1 | -2 (faster) | -1 | -1 | -1 | -1 | -1 |
| Transceiver Data Rate | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps |
Key Differentiators
- Highest-density Arria 10 GX in F40 1517-FCBGA package (vs 10AX066N2F40I1SG)
- Industrial temperature operation across the full family (vs 10AX090N2F40E1SG)
- Hard ARM Cortex-A9 MPCore subsystem on-chip (vs Cyclone 10 GX family)
Design Notes
The 1517-ball FCBGA at 1.0 mm pitch demands a PCB stackup of at least 12 layers with HDI (high-density interconnect) construction. Micro-via arrays must be laser-drilled to escape the inner signal rings. Reference: Intel AN-791 (Arria 10 PCB Design Guidelines). Severity: critical.
Transceiver channels up to 17.4 Gbps require 85-100 ohm differential impedance (100 ohm nominal for most protocols). Maintain intra-pair skew below 1 ps and inter-pair skew below 5 ps. Reference: Intel AN-700 (Arria 10 Transceiver Signal Integrity). Severity: critical.
The Arria 10 GX core supply uses SmartVID and requires a PMBus-compatible regulator such as the Intel EM2K12008 or similar. Decoupling requires 0402-sized 10 nF/100 nF/10 uF arrays on every power rail within 5 mm of the BGA. Reference: Intel AN-789 (Power Distribution Network). Severity: critical.
Estimated: at 25 W total dissipation (typical transceiver-heavy workload) and 1.0 mm FCBGA thermal resistance ~2 C/W to case, junction rises 50C above case - design a heatsink with <0.4 C/W thermal resistance for industrial +100C ambient operation. Severity: recommended.
Do not assume any Arria 10 GX device is pin-compatible with a Stratix V or Cyclone 10 GX - even in the same package. The ball map differs across families, and JTAG, configuration, and SmartVID pin assignments are not preserved. Reference: Intel Arria 10 GX Device Handbook, Volume 1. Severity: critical.
Compliance Information
RoHS and lead-free compliant per Intel product page. AEC-Q100 not applicable (FPGA, not automotive analog IC). Halogen-free status not explicitly stated in web data - set to unknown.
