10AX090N2F40I2SG - Arria 10 GX 900K LE FPGA, 1517-FCBGA | Intel
MPN: 10AX090N2F40I2SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6855.3 | $6,855.30 |
| 5 | $6620.45 | $33,102.25 |
| 10 | $6480.2 | $64,802.00 |
| 25 | $6310.55 | $157,763.75 |
| 50 | $6185 | $309,250.00 |
Drop-in alternatives for 10AX090N2F40I2SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AX090N2F40I2LG
✅ Drop-In✓ In Stock
$6903.28 / Unit
View Datasheet →10AX090N2F40I1SG
✅ Drop-In✓ In Stock
$2985 / Unit
View Datasheet →10AX090N3F40I2SG
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$2250 / Unit
View Datasheet →10AX066N2F40E1SG
✅ Drop-In✓ In Stock
$3350 / Unit
View Datasheet →10AX066K2F40I1SG
✅ Drop-In✓ In Stock
$3395 / Unit
View Datasheet →10AX090N2F40I2SG Maximum Ratings & Electrical Characteristics
| Series | Arria 10 GX |
| Device Family | Arria 10 |
| Logic Elements | 900,000 |
| Number of LABs/CLBs | 339,620 |
| Total RAM Bits | 59,234,304 |
| Number of I/O | 600 |
| Supply Voltage | 0.85 V to 0.95 V core |
| Operating Temperature | -40C to +100C (Industrial) |
| Mounting Type | Surface Mount |
| Package | 1517-BBGA, FCBGA (F40) |
| RoHS Status | Compliant |
| Process Technology | 20 nm TSMC |
| Transceivers | 24 channels, up to 14.1 Gbps |
| Hard Memory Controllers | DDR3/DDR4 (hardened) |
| PCIe Hard IP | PCIe Gen3 x8 |
| Lifecycle Status | Active (per distributor listing) |
10AX090N2F40I2SG 1517-bbga, fcbga (f40) Pin Configuration Guide
Complete pinout information for 10AX090N2F40I2SG (1517-bbga, fcbga (f40) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX090N2F40I2SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX090N2F40I2SG is suitable for 6 applications: 4K/8K Broadcast Video Processing, Wireless Fronthaul / Backhaul (CPRI/OBSAI), Defense Radar and Electronic Warfare, Industrial Machine Vision and Imaging, High-Speed Protocol Bridging (PCIe Gen3 / 10GbE / 100GbE), Test and Measurement Instrumentation.
4K/8K Broadcast Video Processing
The 10AX090N2F40I2SG fits 4K/8K broadcast video processing because its 900K logic elements provide ample DSP and routing resources for multi-stream HEVC/AVC pipelines, while the 24 transceiver lanes (up to 14.1 Gbps) handle SDI-over-fiber or 12G-SDI aggregation without external serializer chips. Per the Arria 10 datasheet, the hardened PCIe Gen3 blocks simplify host-interface DMA engines that move 4K frames at line rate. Designers pair this FPGA with 12G-SDI transceivers and external DDR4 to build broadcast routers that sustain 8K60p throughput within a typical 25W board power envelope.
Recommended
Wireless Fronthaul / Backhaul (CPRI/OBSAI)
The 10AX090N2F40I2SG's 24 transceiver channels map cleanly onto the 6-lane CPRI/OBSAI configurations used in 4G LTE and 5G NR fronthaul, where each radio unit typically requires two or three CPRI links at 9.83 Gbps. The 900K LE fabric implements PHY/MAC baseband plus the IQ compression and packetization required for CPRI Option 7, while the hard memory controllers stream IQ samples into DDR4 buffers. Industrial temperature rating ensures operation in outdoor radio units and base-station chassis; designers should use the Early Power Estimator early because 24 active transceivers can exceed 12W.
Recommended
Defense Radar and Electronic Warfare
The 10AX090N2F40I2SG is well matched to defense radar and electronic-warfare systems because its 900K logic elements plus hundreds of DSP blocks deliver the multiply-accumulate throughput needed for phased-array beamforming and digital down-conversion at IF bandwidths above 100 MHz. The 24 transceivers capture multiple digitized antenna channels at 10 Gbps+ with deterministic latency from the hardened transceivers. Industrial temperature grade (-40C to +100C) supports ground-mobile and shipboard platforms; for airborne or extended-temp missions, designers verify the LG variant in MIL-STD-810 environments.
Recommended
Industrial Machine Vision and Imaging
The 10AX090N2F40I2SG serves industrial machine vision where multiple high-resolution CMOS sensors stream pixel data over CoaXPress, Camera Link, or 10GbE to the FPGA for real-time image processing. Its 24 transceivers aggregate four to six CoaXPress channels at 6.25 Gbps each, while the 900K LE fabric runs ISP pipelines (demosaic, color correction, defect detection) without offloading to a host CPU. Industrial temperature rating and 1517-FCBGA mechanical robustness suit factory-floor vibration; consider the 10AX090N2F40I1SG (speed grade -1) for less timing-aggressive inspection lines.
Recommended
High-Speed Protocol Bridging (PCIe Gen3 / 10GbE / 100GbE)
The 10AX090N2F40I2SG is a strong fit for high-speed protocol bridging in server accelerator cards and embedded computing, where it can simultaneously present a PCIe Gen3 x8 endpoint to a host CPU and bridge to multiple 10GbE or 25GbE links. The hardened PCIe block saves up to 30K LEs versus a soft implementation, freeing fabric for user-defined DMA engines, compression accelerators, or custom coprocessors. Designers use the hard memory controllers for DDR4 buffering of network packets, and the 1517-FCBGA F40 pinout keeps the bridge card to a standard PCIe CEM form factor.
Recommended
Test and Measurement Instrumentation
The 10AX090N2F40I2SG is well suited to test and measurement equipment such as protocol analyzers, logic analyzers, and bit-error-rate testers, where it must acquire multiple high-speed serial lanes and present decoded data to a host in real time. Its 24 transceivers (up to 14.1 Gbps) sample several lanes simultaneously without external retimers, while the 900K LE fabric implements protocol-aware pattern matching, error counters, and trigger logic. The 600 user I/O provide ample connections for front-panel LEDs, displays, and parallel bus interfaces to companion ADCs; pairing with DDR4 captures multi-second traces for protocol debug.
Recommended
Recommended Products Summary
Engineering reference data for 10AX090N2F40I2SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX090N2F40I2LG | 10AX090N2F40I1SG | 10AX090N3F40I2SG | 10AX066N2F40E1SG |
|---|---|---|---|---|---|
| Package | 1517-BBGA, FCBGA (F40) | 1517-BBGA, FCBGA (F40) - same | 1517-BBGA, FCBGA (F40) - same | 1517-BBGA, FCBGA (F40) - same | 1517-BBGA, FCBGA (F40) - same |
| Brand | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 900,000 | 900,000 | 900,000 | 900,000 | 660,000 (-27%) |
| Number of LABs/CLBs | 339,620 | 339,620 | 339,620 | 339,620 | [DATA_NEEDED] |
| Total RAM Bits | 59,234,304 | 59,234,304 | 59,234,304 | 59,234,304 | [DATA_NEEDED] |
| Number of I/O | 600 | 600 | 600 | 600 | 600 |
| Transceivers | 24 channels up to 14.1 Gbps | 24 channels up to 14.1 Gbps | 24 channels up to 14.1 Gbps | 24 channels up to 14.1 Gbps | 24 channels up to 14.1 Gbps |
| Speed Grade | -2 | -2 | -1 (slower) | -3 (faster) | -1 |
| Temperature Grade | Industrial (-40C to +100C) | Industrial (LG suffix) | Industrial | Industrial | Extended (E suffix) |
Key Differentiators
- Industrial temperature grade with lead-free finish (vs 10AX090N2F40I2LG)
- Highest speed grade -2 for tightest transceiver timing (vs 10AX090N2F40I1SG)
- 900K logic elements - 36% more capacity than 10AX066 (vs 10AX066N2F40E1SG)
- Pure programmable logic (no SoC ARM cores) (vs 10AS066K4F35I3SG)
Design Notes
Estimated: at 14.1 Gbps transceiver data rates, plan for a 12-layer PCB with stripline routing for transceiver channels and reference planes within 4 mils of the signal trace. Use 1.0 mm pitch BGA breakout with via-in-pad plated over for the 1517-ball F40 package; an 8-layer PCB typically fails multi-gigabit signal-integrity compliance. Maintain Zdiff = 100 ohm +/-10% for transceiver pairs and Zo = 50 ohm for single-ended signals. Per Intel's Arria 10 PCB design guidelines, allocate at least 4 ground-reference layers adjacent to the F40 footprint.
Estimated: at sustained full fabric and 24 active transceivers, the 10AX090N2F40I2SG can dissipate 18-22W; the FCBGA F40 package requires a heatsink plus forced airflow (at least 200 LFM) to keep junction temperature below 100C. Use Intel's Early Power Estimator (EPE) and PowerPlay during schematic design to size the thermal solution - do not wait for first prototype. Mount a high-performance TIM (such as 3.5 W/m-K gap pad) between package lid and heatsink; the exposed top of the FCBGA is the primary thermal path.
Do not confuse the Arria 10 GX (10AX) with the Arria 10 SoC (10AS) - the SoC variants integrate a dual-core ARM Cortex-A9 hard processor system but share the F40 package footprint only on selected SKUs. Verify the exact ordering part number against the Intel Arria 10 ordering information document before layout, because confusing 10AX with 10AS produces a board that appears to power up but fails to configure. Also verify the suffix (SG vs LG vs HG) matches the temperature and lead-free finish required by your compliance regime.
Estimated: typical power for the 10AX090N2F40I2SG at 70-80% logic utilization with 12 active transceivers ranges from 14W to 18W. Provide a minimum of 3 separate supply rails (VCC, VCCP/VCCPT for transceiver PLL, and VCCIO for I/O banks) each decoupled with a 220uF bulk plus 22uF and 100nF ceramic capacitors within 5mm of each supply ball. The transceiver PLLs are particularly sensitive to noise - isolate them on a quiet ground plane and avoid running switching signals under the F40 footprint's PLL region.
Place configuration flash (such as EPCQ-L256) within 6 inches of the FPGA on the same PCB layer to avoid signal-integrity issues during FPGA configuration. Use differential 100 ohm routing for the configuration clock DCLK and data lines, and provide a JTAG header accessible from the board edge for boundary-scan and Quartus Prime programmer access. If the design uses multiple FPGAs, the Arria 10 supports x1, x4, and x8 configuration modes; verify pin assignments against Intel's configuration user guide before committing layout.
Compliance Information
RoHS compliant per distributor listing and Intel Arria 10 product family compliance page. AEC-Q100 is not applicable to FPGAs; for automotive applications, see Intel's Cyclone V / Cyclone 10 family that targets AEC-Q100.
