10AX090R2F40E1SG - Arria 10 GX 900K LE FPGA, 1517-FCBGA | Intel
MPN: 10AX090R2F40E1SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8102.99 | $8,102.99 |
| 10 | $7600 | $76,000.00 |
| 100 | $6800 | $680,000.00 |
| 500 | $6200 | $3,100,000.00 |
| 1,000 | $5750 | $5,750,000.00 |
Drop-in alternatives for 10AX090R2F40E1SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →10AX090R2F40E1SG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements (LE) | 900,000 |
| Embedded Memory Bits | 59,234,304 |
| User I/O Count | 342 |
| Max Transceiver Data Rate | 28.3 Gbps |
| Hard Memory Controllers | Yes |
| Hard PCIe Gen3 IP | Yes (x8) |
| Hard 100G Ethernet MAC | Yes |
| Process Technology | 20 nm |
| Core Voltage | 0.9 V |
| Operating Temperature Grade | Enhanced (E1) |
| Package | 1517-ball FCBGA (F40), 40 x 40 mm |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| Lead-Free | Yes |
10AX090R2F40E1SG 1517-ball fcbga (f40), 40 x 40 mm Pin Configuration Guide
Complete pinout information for 10AX090R2F40E1SG (1517-ball fcbga (f40), 40 x 40 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX090R2F40E1SG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AX090R2F40E1SG is suitable for 6 applications: 100G Ethernet Line Card, OTN / DWDM Transponder and Muxponder, Military Radar and SIGINT Signal Processing, ASIC Prototyping and Emulation, Broadcast Video Processing and HDR Conversion, Medical Imaging and Ultrasound Beamforming.
100G Ethernet Line Card
The 10AX090R2F40E1SG's hard 100G Ethernet MAC IP and 28.3 Gbps transceiver channels make it ideal for 100G line-card designs. With four transceivers at 25.78 Gbps plus the hardened MAC, designers implement a full 100G MAC-to-physical layer datapath with minimal soft-logic area. The 59 Mbit embedded memory buffers packet bursts without external buffering, and the 1517-FCBGA's thermal lid enables high-wattage operation with a passive or active heatsink.
Recommended
OTN / DWDM Transponder and Muxponder
The 10AX090R2F40E1SG supports OTU4 (111.8 Gbps) and OTUCn (n=1..4) framing with hard IP blocks that significantly simplify the framer datapath. Hard PCS lanes and adaptive transceiver equalization drive long-reach optical modules and 10 km DWDM links directly. The device's enhanced temperature grade (E1) suits central-office deployment where ambient remains stable.
Recommended
Military Radar and SIGINT Signal Processing
Radar baseband and SIGINT systems require heavy floating-point DSP, large FFT windows, and parallel channel processing. The Arria 10 variable-precision DSP blocks and 900K LE fabric in the 10AX090R2F40E1SG implement complex FFTs and beam-forming arrays at full sample rate. The 20 nm process and hard PCIe Gen3 IP enable direct attachment to host CPUs or DSP cards with deterministic latency.
Recommended
ASIC Prototyping and Emulation
The 10AX090R2F40E1SG's 900K logic elements and abundant M20K memory make it a strong fit for ASIC prototyping at sub-100M gate complexity. Designers partition RTL across multiple Arria 10 devices via the embedded transceivers, achieving multi-FPGA prototyping with several hundred MHz system clock. Quartus Prime Pro supports time-domain multiplexing and pin multiplexing for fast bring-up.
Recommended
Broadcast Video Processing and HDR Conversion
4K/8K broadcast pipelines require high frame-rate video color-space conversion, HDR/WCG tone mapping, and multi-channel scaling. The 10AX090R2F40E1SG's embedded memory and DSP blocks handle simultaneous 4:2:2/4:4:4/4:2:0 conversion across multiple 4K streams at 60p. The hard memory controller interfaces with DDR4 banks used for line and frame buffers.
Recommended
Medical Imaging and Ultrasound Beamforming
Ultrasound systems drive 64-256 channels of beamforming at 40-80 MSPS, with front-end ADC data piped into the FPGA for delay-and-sum processing. The 10AX090R2F40E1SG's high-speed transceivers link to ADC front ends, and the floating-point DSP blocks compute beamformed image frames. The hard PCIe Gen3 IP delivers image data to host processors in real time, supporting 4D ultrasound and elastography.
Recommended
Recommended Products Summary
Engineering reference data for 10AX090R2F40E1SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX090R1F40E1SG | 10AX090R1F40I1SG | 10AX090N3F40I2LG | 10AX090N4F45I3LG | 10AX066N2F40E1SG |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 1517-FCBGA (F40) | 1517-FCBGA (F40) - same | 1517-FCBGA (F40) - same | 1517-FCBGA (F40) - same | 1517-FCBGA (F45) - LARGER 45x45mm | 1517-FCBGA (F40) - same |
| Logic Elements | 900,000 | 900,000 (same) | 900,000 (same) | 900,000 (same) | 900,000 (same) | 660,000 (-27%) |
| Transceiver Tier (R/N suffix) | R2 (mid-range) | R1 (lower channel count) | R1 (lower channel count) | N3 (higher channel count) | N4 (highest channel count) | N2 (higher channel count) |
| Max Transceiver Data Rate | 28.3 Gbps | 28.3 Gbps (same) | 28.3 Gbps (same) | 28.3 Gbps (same) | 28.3 Gbps (same) | 28.3 Gbps (same) |
| Temperature Grade | Enhanced (E1) -20C to 100C | Enhanced (E1) - same | Industrial (I1) -40C to 100C | Industrial (I2) | Industrial (I3) | Enhanced (E1) |
| Embedded Memory Bits | 59,234,304 | 59,234,304 (same) | 59,234,304 (same) | 59,234,304 (same) | 59,234,304 (same) | Lower density (~40M bits) |
| Process Technology | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm | 20 nm |
Key Differentiators
- R2 transceiver tier balances cost and channel count for mid-range 100G designs (vs 10AX090N3F40I2LG)
- 900K LE density at lower cost than higher-tier density equivalents (vs 10AX090N4F45I3LG)
- Enhanced (E1) temperature grade targets telecom/datacom controlled environments (vs 10AX090R2F40I1SG)
Design Notes
The 1517-FCBGA package exposes the die through a metal lid that accepts thermal interface material (TIM) and a heatsink. Estimated: at 40 W total dissipation and a heatsink theta_SA of 0.5 C/W with TIM, junction-to-ambient rise is approximately 31 C above ambient for the E1 grade. A heatpipe solution or low-velocity forced-air cooling is recommended for ambient temperatures approaching 60 C. Always validate with the Intel PowerPlay tool post-place-and-route.
Multiple supply rails are required: 0.9 V core, 1.8 V analog PLL supplies, and dedicated transceiver rails (typically 1.0 V and 1.5 V depending on channel rate). Decoupling must include 0402-size 100 nF and 10 uF bulk ceramics within 2 mm of each power pin, plus board-level bulk capacitors at voltage regulator outputs. Power sequencing is enforced by the Intel reference design - assert 0.9 V before 1.8 V to prevent latch-up.
The 40 x 40 mm FCBGA requires a high-layer-count PCB (typically 16+ layers) with stacked microvia-in-pad construction for breakout. Recommended stackup uses 1-oz outer copper on standard FR-4 with Megtron-6 or equivalent low-Df material near the package. Matched-length tuning for transceiver lanes (within +/- 2 ps skew differential) is essential at 28 Gbps.
Group transceivers in dedicated bank regions to minimize via stubs and return-path discontinuity. The transceiver reference clock pin requires a low-jitter source (sub-300 fs RMS) with a series ferrite bead for power-rail noise isolation. Route LVDS pairs in 100 ohm differential impedance and keep away from switching power supply edges.
Do not enable more LVDS pairs per bank than the VCCIO rail can source - each pair draws ~7 mA and excessive load degrades signal integrity. Always configure unused I/O banks to a defined state via Quartus Pin Planner to avoid floating-pin leakage. Configuration mode (JTAG, AS, PS) and MSEL pins must be set correctly at PCB boot or the device will fail to configure.
Compliance Information
RoHS and lead-free per ampheo.com product listing. Not AEC-Q100 qualified - this is a commercial/industrial-grade part.
