10AX090R2F40I2SG - Arria 10 GX FPGA 90K LE | Intel (Altera)
MPN: 10AX090R2F40I2SG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7474.06 | $7,474.06 |
| 10 | $7175.45 | $71,754.50 |
| 100 | $6812.9 | $681,290.00 |
| 500 | $6532.1 | $3,266,050.00 |
| 1,000 | $6290.55 | $6,290,550.00 |
10AX090R2F40I2SG Overview
What is an FPGA? A field-programmable gate array is a reconfigurable semiconductor device containing an array of programmable logic blocks, configurable interconnect, and hardened IP such as transceivers, DSP blocks, and memory controllers. FPGAs occupy the hierarchy between application-specific integrated circuits (ASICs) and general-purpose processors, offering hardware-level parallelism with software-level reprogrammability. The Arria 10 family uses TSMC's 20 nm process and integrates 28 Gbps transceivers, hardened floating-point DSP, and partial reconfiguration for power-efficient acceleration.
Key features of the 10AX090R2F40I2SG include 900K logic elements (LEs), 3,748 embedded 18x19 multipliers, 1,517-pin FCBGA package (40x40 mm), industrial temperature grade (-40C to +100C TJ), and 28.05 Gbps transceiver support. The device also provides 342 user I/O, 1,518 user I/O pins per package, and supports up to 240 high-speed serial links when fully populated. Core voltage is 0.87V to 0.98V.
The Arria 10 GX architecture combines a hard silicon implementation of dual ARM Cortex-A9 cores for system management, hard PCI Express Gen3 controllers, and hard memory controllers. The 28.05 Gbps transceivers support backplane and chip-to-chip optical links, while the variable-precision DSP blocks enable IEEE 754 single-precision floating-point at up to 1.5 TFLOPs. This integration dramatically reduces system BOM and power versus building equivalent functions from soft logic.
Typical applications include 100G/400G optical line cards, 4G/5G LTE baseband processing, ASIC prototyping, high-performance computing accelerators, broadcast video processing, and military secure communications. The integrated transceivers make it particularly suited for telecom line cards where BOM consolidation is critical.
When designing with this device, ensure the PCB has a minimum 12-layer stack-up with buried capacitance to meet the 28 Gbps signal-integrity envelope. Power-supply sequencing must follow the Intel Enpirion power-tree reference to prevent inrush damage. JTAG and MSEL configuration pins must be strapped per the Intel Arria 10 GX handbook before bitstream load.
This page synthesizes distributor pricing, drop-in Intel same-family alternatives, and design considerations not found in the bare manufacturer datasheet. Engineers can compare 10AX090R2F40I2SG against same-package speed/grade variants using the comparison_table below.
Drop-in alternatives for 10AX090R2F40I2SG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with 10AX090R2F40I2SG (same form factor and footprint) — differing in Package, Mounting Type, Temperature Grade, Speed Grade, Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AX090R2F40I2LG
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →10AX090R2F40I1SG
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$3720 / Unit
View Datasheet →10AX090R2F40E2SG
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$4750 / Unit
View Datasheet →10AX090R2F40E2LG
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$2920 / Unit
View Datasheet →10AX090R2F40E1SG
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$5750 / Unit
View Datasheet →10AX090R1F40I1SG
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$3783 / Unit
View Datasheet →10AX090R1F40E1SG
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$6700 / Unit
View Datasheet →10AX090R2F40I2SG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 GX |
| Logic Elements (LEs) | 900,000 |
| Embedded Memory (bits) | 59,234,304 |
| Adaptive Logic Modules (ALMs) | 342,000 |
| DSP Blocks | 1,518 |
| 18x19 Multipliers | 3,748 |
| Transceiver Count | 24 (28.05 Gbps) |
| Maximum User I/O | 342 |
| Package | 1517-BBGA, FCBGA (40x40 mm) |
| Core Voltage | 0.87 V to 0.98 V |
| Operating Temperature | -40C to +100C (TJ) |
| Temperature Grade | Industrial |
| Mounting Type | Surface Mount |
| Process Node | TSMC 20 nm |
| RoHS Status | Compliant |
10AX090R2F40I2SG 1517-bbga, fcbga (40x40 mm) Pin Configuration Guide
Pin configuration for 10AX090R2F40I2SG (1517-bbga, fcbga (40x40 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AX090R2F40I2SG.
Refer to the datasheet for full pin configuration.
Typical Applications
10AX090R2F40I2SG is suitable for 7 applications: 100G/400G Optical Transport Line Card, 5G/LTE Baseband Processing, ASIC Prototyping and Emulation, High-Performance DSP / Radar Processing, Broadcast Video Processing, Test & Measurement Instrumentation, Aerospace & Defense Secure Communications.
100G/400G Optical Transport Line Card
The 10AX090R2F40I2SG fits 100G/400G optical line cards because its 24 transceivers at 28.05 Gbps natively drive CFP4/CFP2-DCO coherent optics, OTU4 long-haul framers, and 100GbE KR4 backplanes without external SerDes. With 900K LEs and 1,518 DSP blocks, the device can run IEEE 802.3bj FEC (KP4) soft-decision forward error correction in real time while simultaneously managing OTN framing and MACsec encryption. The 1517-ball F40 package exposes all transceiver channels, making it ideal for OTN muxponder designs where 4x28G to 1x100G aggregation is required. Power dissipation for a fully loaded 100G line card is approximately 35-40 W at 0.95V core.
Recommended
5G/LTE Baseband Processing
The 10AX090R2F40I2SG is well suited for 4G LTE-Advanced Pro and 5G NR baseband units because its 1,518 variable-precision DSP blocks deliver up to 1.5 TFLOPs of IEEE 754 single-precision floating-point, enough to process 6 downlink layers + 4 uplink layers of a 100 MHz 5G NR carrier on a single device. The 24 transceivers connect to RRH fronthaul (CPRI-7/eCPRI) at 24.33 Gbps, supporting massive MIMO antenna arrays. The hard ARM Cortex-A9 subsystem handles L2/L3 protocol stack, while the FPGA fabric runs the PHY/FFT/precoding. Industrial temperature grade supports outdoor small-cell deployments.
Recommended
ASIC Prototyping and Emulation
The 10AX090R2F40I2SG is widely deployed in commercial ASIC prototyping platforms because its 900K LEs map large ASIC RTL partitions (typically 5-10M ASIC gates equivalent) with debug visibility. The high I/O count (342 user I/O plus 24 transceivers) supports prototyping of SoCs with multiple memory interfaces, PCIe Gen3, and SerDes. Designers use the partial-reconfiguration feature to swap RTL blocks in seconds, accelerating bring-up vs. traditional FPGA emulation. Industrial temperature grade enables operation in chassis that exceed ambient datacenter temperatures during burn-in.
Recommended
High-Performance DSP / Radar Processing
The 10AX090R2F40I2SG accelerates radar, electronic warfare, and scientific DSP because its 1,518 DSP blocks deliver 1.5 TFLOPs of single-precision floating point, sufficient to process multi-channel phased-array radar FFTs, synthetic aperture radar (SAR) back-projection, and adaptive beamforming in real time. The 59 Mbit embedded memory sustains high FFT throughput without external memory round-trips. Military/aerospace designers choose the industrial temperature variant for airborne and shipboard radar platforms.
Recommended
Broadcast Video Processing
The 10AX090R2F40I2SG fits broadcast video processing because its 900K LEs can ingest 4x 12G-SDI streams (12 Gbps each) via the transceivers and run multi-stream HEVC/H.264 encoding/decoding, color-space conversion, and on-screen graphics blending simultaneously. The hard PCIe Gen3 endpoint connects to host video servers, while the large embedded memory sustains multiple frame buffers. Industrial temperature grade supports server-room environments with limited cooling.
Recommended
Test & Measurement Instrumentation
The 10AX090R2F40I2SG is used in high-end test & measurement equipment because its 24 transceivers support multi-lane protocol analyzers for PCIe Gen4, USB 3.2, SAS-4, and 100GbE traffic capture and generation. The 900K LEs enable deep trace memory, protocol state machines, and real-time protocol decoding. Industrial temperature grade supports benchtop and rack-mounted test gear in lab environments. JTAG and partial reconfiguration enable fast pattern updates during conformance testing.
Recommended
Aerospace & Defense Secure Communications
The 10AX090R2F40I2SG fits military secure communications because its 28 Gbps transceivers drive tactical radio waveforms, anti-jam GPS processing, and Type-1 crypto acceleration. The 900K LEs can implement multi-channel SATCOM modems, LINK-16/MIDS terminals, and adaptive signal processing for LPI/LPD waveforms. Industrial-extended temperature grade supports harsh-environment mil-aero platforms. The Arria 10 architecture has been certified for MIL-STD-810 and DO-160 in many defense platforms.
Recommended
Recommended Products Summary
Engineering reference data for 10AX090R2F40I2SG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AX090R2F40I2LG | 10AX090R2F40I1SG | 10AX090R2F40E2SG | 10AX090R2F40E2LG | 10AX090R2F40E1SG |
|---|---|---|---|---|---|---|
| Package | 1517-FCBGA (40x40 mm, F40) | 1517-FCBGA (40x40 mm, F40) - same | 1517-FCBGA (40x40 mm, F40) - same | 1517-FCBGA (40x40 mm, F40) - same | 1517-FCBGA (40x40 mm, F40) - same | 1517-FCBGA (40x40 mm, F40) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 | 900,000 |
| Speed Grade | 2 | 2 | 1 | 2 | 2 | 1 |
| Temperature Grade | Industrial (-40C to +100C) | Extended Industrial (-40C to +125C TJ) | Industrial (-40C to +100C) | Commercial (0C to +100C) | Commercial Extended | Commercial (0C to +100C) |
| Transceiver Count | 24 (28.05 Gbps) | 24 | 24 | 24 | 24 | 24 |
| Core Voltage | 0.87 V to 0.98 V | 0.87 V to 0.98 V | 0.87 V to 0.98 V | 0.87 V to 0.98 V | 0.87 V to 0.98 V | 0.87 V to 0.98 V |
| Pinout / Footprint | F40 (40x40 mm FCBGA) | F40 - drop-in compatible | F40 - drop-in compatible | F40 - drop-in compatible | F40 - drop-in compatible | F40 - drop-in compatible |
Key Differentiators
- Higher transceiver count than R1 variants in same package (vs 10AX090R1F40I1SG)
- Speed grade 2 offers ~15% higher Fmax than grade 1 (vs 10AX090R2F40I1SG)
- Industrial temperature grade vs commercial (vs 10AX090R2F40E2SG)
- Same F40 footprint enables PCB reuse across temp/speed variants (vs 10AX090N3F40I2SG (no-transceiver variant))
- 900K LE in Arria 10 vs 660K LE in Arria 10 SX (10AS066) (vs 10AS066K4F35I3SG)
Design Notes
Estimated: The 10AX090R2F40I2SG core supply at 0.95 V can draw up to 35-45 A during full utilization (900K LE at 85% toggle rate, all transceivers active). Use Intel Enpirion EM2130 or EM21xx digital controller + dual-phase DrMOS power stage with at least 4-layer PCB power planes. Power-on sequencing must follow Intel Arria 10 GX handbook sequence: 3.3V -> 2.5V -> 1.8V -> 0.95V core -> PLL supplies. Any deviation can cause inrush latch-up. Decoupling: place 0402 0.1 uF X7R on every 6th ball row, plus 47 uF polymer bulk per quadrant.
The 1517-ball FCBGA requires a 12-layer PCB minimum with stacked-via or HDI construction to break out the 1 mm pitch BGA. Each quadrant of the package is 22.5x22.5 mm with full BGA escape requiring 4 signal layers + 1 ground layer per quadrant. Use Megtron-6 or equivalent low-loss dielectric with Dk=3.4 at 10 GHz for 28 Gbps channel integrity. Total PCB thickness target: 1.55-2.0 mm. Microstrip-to-stripline transitions must use ground-via fencing within 200 um of signal via.
Estimated: Full-load power dissipation is 30-40 W typical at industrial temperature, requiring a thermal solution with theta_JA < 5 C/W. Recommended heat sink: 35x35 mm aluminum pin-fin with 1.5 m/s airflow, OR a custom cold plate for sealed enclosures. Junction-to-case thermal resistance (theta_JC) of the F40 package is approximately 0.15 C/W - the heat-sink TIM should be a 50 um indium foil or Shin-Etsu X-23-7921-5. Without airflow, junction temperature will exceed 100C within 5 minutes at full utilization.
28 Gbps transceivers require strict signal-integrity discipline. PCB trace loss must be < 1.5 dB/inch at 14 GHz Nyquist; use Megtron-6 PCB or better. Reference plane continuity must be maintained across all layers; do NOT route signals across plane splits. AC-coupling capacitors on transmit paths must be 100 nF 0402 X7R placed within 200 mil of the BGA ball. Receiver CTLE and adaptive equalization are configured via the Arria 10 GX transceiver toolkit - run IBIS-AMI simulations before tape-out.
Common pitfalls with 10AX090R2F40I2SG designs: (1) Forgetting MSEL configuration straps - the device will not configure without correct MSEL[4:0] setting; (2) Using a single JTAG chain for multiple devices without a TDO-to-TDI buffer; (3) Not connecting nCONFIG, nSTATUS, and CONF_DONE to a pull-up - configuration will fail on power-up glitches; (4) Using the wrong Quartus Prime device variant in the project - this disables transceivers and DSP; (5) Powering the device before the bitstream is loaded into the EPCQ configuration flash - causes 50-100 ms inrush at every POR.
Compliance Information
RoHS compliant and lead-free per Intel product page. AEC-Q100 not applicable (FPGA not an automotive IC). Intel is a member of the Responsible Minerals Initiative; conflict-minerals statement available on Intel corporate site.
