10CL010YE144C6G - Cyclone 10 LP FPGA 10K LE, 144-LQFP | Altera/Intel
MPN: 10CL010YE144C6G β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4.18 | $4.18 |
| 10 | $3.82 | $38.20 |
| 100 | $3.35 | $335.00 |
| 500 | $2.95 | $1,475.00 |
| 1,000 | $2.6 | $2,600.00 |
Drop-in alternatives for 10CL010YE144C6G β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
10CL010YE144C8G
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View Datasheet β10CL010YE144A7G
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View Datasheet β10CL006YE144C6G
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$8.15 / Unit
View Datasheet β10CL006YE144C8G
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$41.25 / Unit
View Datasheet β10CL006YE144A7G
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$17.4 / Unit
View Datasheet β10CL006ZE144I8G
β Drop-Inβ In Stock
$35.88 / Unit
View Datasheet β10CL006ZE144I7G
β Drop-Inπ Reference alternative (not in catalog)
10CL010YE144C6G Maximum Ratings & Electrical Characteristics
| Family | Cyclone 10 LP |
| Series | Cyclone 10 |
| Device Model | 10CL010 |
| Logic Elements (LE) | 10,320 |
| Embedded Memory | 423,936 bits (M9K blocks) |
| User I/O Count | 88 |
| Package | 144-LQFP Exposed Pad (EQFP-144) |
| Speed Grade | 6 |
| Temperature Grade | Commercial (C) |
| Process Technology | TSMC 60 nm low-power |
| Number of Pins | 144 |
| Mounting Type | Surface Mount |
| Programmable Logic Type | FPGA (in-system programmable via SRAM) |
| Configuration Method | Active serial (AS), passive serial (PS), JTAG |
| Operating Temperature Range | 0C to +85C (commercial) |
| RoHS Status | Compliant |
| MSL Level | 3 (per JEDEC J-STD-020) |
10CL010YE144C6G Pin Configuration
| Pin 1 | I/O β User I/O bank 1 |
| Pin 2 | I/O β User I/O bank 1 |
| Pin 3 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 4 | I/O β User I/O bank 1 |
| Pin 5 | I/O β User I/O bank 1 |
| Pin 6 | GND β Ground |
| Pin 7 | I/O β User I/O bank 1 |
| Pin 8 | I/O β User I/O bank 1 |
| Pin 9 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 10 | I/O β User I/O bank 1 |
| Pin 11 | I/O β User I/O bank 1 |
| Pin 12 | GND β Ground |
| Pin 13 | I/O β User I/O bank 2 |
| Pin 14 | I/O β User I/O bank 2 |
| Pin 15 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 16 | I/O β User I/O bank 2 |
| Pin 17 | I/O β User I/O bank 2 |
| Pin 18 | GND β Ground |
| Pin 19 | I/O β User I/O bank 2 |
| Pin 20 | I/O β User I/O bank 2 |
| Pin 21 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 22 | I/O β User I/O bank 2 |
| Pin 23 | I/O β User I/O bank 2 |
| Pin 24 | GND β Ground |
| Pin 25 | I/O β User I/O bank 3 |
| Pin 26 | I/O β User I/O bank 3 |
| Pin 27 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 28 | I/O β User I/O bank 3 |
| Pin 29 | I/O β User I/O bank 3 |
| Pin 30 | GND β Ground |
| Pin 31 | I/O β User I/O bank 3 |
| Pin 32 | I/O β User I/O bank 3 |
| Pin 33 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 34 | I/O β User I/O bank 3 |
| Pin 35 | I/O β User I/O bank 3 |
| Pin 36 | GND β Ground |
| Pin 37 | I/O β User I/O bank 4 |
| Pin 38 | I/O β User I/O bank 4 |
| Pin 39 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 40 | I/O β User I/O bank 4 |
| Pin 41 | I/O β User I/O bank 4 |
| Pin 42 | GND β Ground |
| Pin 43 | I/O β User I/O bank 4 |
| Pin 44 | I/O β User I/O bank 4 |
| Pin 45 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 46 | I/O β User I/O bank 4 |
| Pin 47 | I/O β User I/O bank 4 |
| Pin 48 | GND β Ground |
| Pin 49 | I/O β User I/O bank 5 |
| Pin 50 | I/O β User I/O bank 5 |
| Pin 51 | VCCIO5 β I/O bank 5 supply voltage |
| Pin 52 | I/O β User I/O bank 5 |
| Pin 53 | I/O β User I/O bank 5 |
| Pin 54 | GND β Ground |
| Pin 55 | I/O β User I/O bank 5 |
| Pin 56 | I/O β User I/O bank 5 |
| Pin 57 | VCCIO5 β I/O bank 5 supply voltage |
| Pin 58 | I/O β User I/O bank 5 |
| Pin 59 | I/O β User I/O bank 5 |
| Pin 60 | GND β Ground |
| Pin 61 | I/O β User I/O bank 6 |
| Pin 62 | I/O β User I/O bank 6 |
| Pin 63 | VCCIO6 β I/O bank 6 supply voltage |
| Pin 64 | I/O β User I/O bank 6 |
| Pin 65 | I/O β User I/O bank 6 |
| Pin 66 | GND β Ground |
| Pin 67 | I/O β User I/O bank 6 |
| Pin 68 | I/O β User I/O bank 6 |
| Pin 69 | VCCIO6 β I/O bank 6 supply voltage |
| Pin 70 | I/O β User I/O bank 6 |
| Pin 71 | I/O β User I/O bank 6 |
| Pin 72 | GND β Ground |
| Pin 73 | I/O β User I/O bank 7 |
| Pin 74 | I/O β User I/O bank 7 |
| Pin 75 | VCCIO7 β I/O bank 7 supply voltage |
| Pin 76 | I/O β User I/O bank 7 |
| Pin 77 | I/O β User I/O bank 7 |
| Pin 78 | GND β Ground |
| Pin 79 | I/O β User I/O bank 7 |
| Pin 80 | I/O β User I/O bank 7 |
| Pin 81 | VCCIO7 β I/O bank 7 supply voltage |
| Pin 82 | I/O β User I/O bank 7 |
| Pin 83 | I/O β User I/O bank 7 |
| Pin 84 | GND β Ground |
| Pin 85 | I/O β User I/O bank 8 |
| Pin 86 | I/O β User I/O bank 8 |
| Pin 87 | VCCIO8 β I/O bank 8 supply voltage |
| Pin 88 | I/O β User I/O bank 8 |
| Pin 89 | I/O β User I/O bank 8 |
| Pin 90 | GND β Ground |
| Pin 91 | I/O β User I/O bank 8 |
| Pin 92 | I/O β User I/O bank 8 |
| Pin 93 | VCCIO8 β I/O bank 8 supply voltage |
| Pin 94 | I/O β User I/O bank 8 |
| Pin 95 | I/O β User I/O bank 8 |
| Pin 96 | GND β Ground |
| Pin 97 | I/O β User I/O bank 1/2 |
| Pin 98 | I/O β User I/O bank 1/2 |
| Pin 99 | I/O β User I/O bank 1/2 |
| Pin 100 | I/O β User I/O bank 1/2 |
| Pin 101 | VCCINT β Core logic supply voltage (1.2 V typical) |
| Pin 102 | I/O β User I/O bank 1/2 |
| Pin 103 | I/O β User I/O bank 1/2 |
| Pin 104 | I/O β User I/O bank 1/2 |
| Pin 105 | I/O β User I/O bank 1/2 |
| Pin 106 | VCCINT β Core logic supply voltage |
| Pin 107 | I/O β User I/O bank 1/2 |
| Pin 108 | I/O β User I/O bank 1/2 |
| Pin 109 | GND β Ground |
| Pin 110 | I/O β User I/O bank 1/2 |
| Pin 111 | I/O β User I/O bank 1/2 |
| Pin 112 | I/O β User I/O bank 1/2 |
| Pin 113 | I/O β User I/O bank 1/2 |
| Pin 114 | VCCA β PLL analog supply voltage |
| Pin 115 | I/O β User I/O bank 1/2 |
| Pin 116 | I/O β User I/O bank 1/2 |
| Pin 117 | I/O β User I/O bank 1/2 |
| Pin 118 | I/O β User I/O bank 1/2 |
| Pin 119 | GND β Ground |
| Pin 120 | I/O β User I/O bank 1/2 |
| Pin 121 | I/O β User I/O bank 1/2 |
| Pin 122 | nSTATUS β Configuration status (open-drain) |
| Pin 123 | CONFIG_DONE β Configuration complete (open-drain) |
| Pin 124 | nCONFIG β Configuration start (active-low) |
| Pin 125 | TMS β JTAG Test Mode Select |
| Pin 126 | TCK β JTAG Test Clock |
| Pin 127 | TDO β JTAG Test Data Out |
| Pin 128 | TDI β JTAG Test Data In |
| Pin 129 | MSEL0 β Configuration mode select 0 |
| Pin 130 | MSEL1 β Configuration mode select 1 |
| Pin 131 | MSEL2 β Configuration mode select 2 |
| Pin 132 | GND β Ground |
| Pin 133 | DCLK β Configuration clock input |
| Pin 134 | DATA0 β Configuration data input |
| Pin 135 | I/O β User I/O bank 1/2 |
| Pin 136 | I/O β User I/O bank 1/2 |
| Pin 137 | I/O β User I/O bank 1/2 |
| Pin 138 | I/O β User I/O bank 1/2 |
| Pin 139 | VCCIO1/2 β I/O bank supply voltage |
| Pin 140 | I/O β User I/O bank 1/2 |
| Pin 141 | I/O β User I/O bank 1/2 |
| Pin 142 | I/O β User I/O bank 1/2 |
| Pin 143 | I/O β User I/O bank 1/2 |
| Pin 144 | GND β Ground (center pin / exposed pad also GND) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CL010YE144C6G is suitable for 7 applications: Industrial I/O Expansion Module, Motor Control and Drive Board, Video Format Converter / Bridge, Low-Cost Protocol Bridge (UART/SPI/I2C), LED Display Controller, Portable Test & Measurement Instrument, I/O Expansion Companion to Host Processor.
Industrial I/O Expansion Module
The 10CL010YE144C6G is well suited to industrial I/O expansion modules that need to aggregate multiple bus interfaces and condition GPIO. Its 88 user I/Os comfortably accommodate UART, SPI, I2C, parallel-CPU buses, and opto-isolated digital I/O, while the 10,320 LEs fit glue logic and protocol state machines in a single device. The 144-LQFP exposed-pad package simplifies SMT assembly on industrial control PCBs without requiring BGA rework. Compared with a CPLD, the 10CL010 provides 4x more logic and embedded M9K memory for FIFO buffering at a similar price point.
Recommended
Motor Control and Drive Board
In low-voltage motor drive designs the 10CL010YE144C6G serves as the control FPGA, generating PWM signals, sampling encoder feedback, and executing field-oriented-control (FOC) loops. Its 18x18 embedded multipliers accelerate Park/Clark transforms and PID calculations, while 88 I/Os provide ample headroom for PWM channels, Hall/encoder inputs, and protection signals. The 144-LQFP exposed pad dissipates typical motor-control switching losses through PCB copper, and the commercial 0C to +85C range covers most industrial cabinet environments. Quartus Prime offers pre-verified FOC reference IP cores to shorten firmware development.
Recommended
Video Format Converter / Bridge
The 10CL010YE144C6G fits low-cost video bridging applications such as BT.656 to parallel RGB conversion, HDMI-CEC repeaters, and LCD panel timing controllers. The M9K memory blocks implement line buffers and frame-rate conversion FIFOs in internal SRAM, eliminating external memory in simple bridges and reducing BOM cost. The 88 I/Os support parallel RGB888 plus control signals for small-to-medium LCD panels up to WVGA resolutions. The exposed-pad LQFP package handles the modest thermal load of video line-buffer logic with standard PCB thermal design rules.
Recommended
Low-Cost Protocol Bridge (UART/SPI/I2C)
The 10CL010YE144C6G is ideal for protocol bridge designs that translate between UART, SPI, I2C, RS-485, CAN, and custom parallel buses in industrial gateways and point-of-sale terminals. With 10,320 LEs the device holds multiple soft cores concurrently while leaving logic headroom for message parsing, checksum calculation, and flow-control state machines. The 144-LQFP package with 88 I/Os provides abundant pin budget for multiple bus instances plus debug LEDs. Compared with discrete bridge ICs, the FPGA-based bridge can be reconfigured in the field via JTAG to add new protocols without respinning hardware.
Recommended
LED Display Controller
The 10CL010YE144C6G drives small-to-medium full-color LED matrix displays by generating multiplexing waveforms, gamma correction tables, and refresh control logic. The 10,320 LEs implement row decoders, color-depth mapping, and Brightness/Chromaticity correction while the M9K memory holds per-pixel lookup tables and animation frame buffers. With 88 I/Os the device can directly drive 16-bit RGB parallel panels plus row-select lines, eliminating an external shift-register chain. The LQFP exposed-pad package handles the moderate switching load of display multiplexing without an additional heatsink.
Recommended
Portable Test & Measurement Instrument
The 10CL010YE144C6G acts as the capture and processing core in portable oscilloscope data loggers, logic analyzers, and protocol testers. Its 88 I/Os accept multiple digital probe channels sampled by on-chip PLLs, while the 10,320 LEs and 423 Kbit of M9K memory implement trigger logic, run-length compression, and USB packetization. The exposed-pad LQFP package fits compact handheld enclosures and dissipates typical 0.5 to 1 W logic loads through PCB copper without active cooling. Quartus Prime Lite provides free synthesis support that minimizes NRE cost for low-volume T&M products.
Recommended
I/O Expansion Companion to Host Processor
The 10CL010YE144C6G is widely deployed as a low-cost I/O expansion companion to ARM-based host processors in point-of-sale terminals, kiosk controllers, and industrial HMIs. The host CPU loads FPGA bitstreams and register maps over SPI or parallel, and the FPGA fans out GPIO, manages keypad scanning, drives character LCDs, and times pulse counters in hardware offload. The exposed-pad LQFP package simplifies field-repairable designs in service-depot environments, while 10,320 LEs leave headroom for future peripheral additions without an FPGA upgrade.
Recommended
Recommended Products Summary
Engineering reference data for 10CL010YE144C6G β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CL010YE144C8G | 10CL010YE144A7G | 10CL006YE144C6G | 10CL006YE144C8G | 10CL006YE144A7G |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 144-LQFP Exposed Pad | 144-LQFP Exposed Pad - same | 144-LQFP Exposed Pad - same | 144-LQFP Exposed Pad - same | 144-LQFP Exposed Pad - same | 144-LQFP Exposed Pad - same |
| Logic Elements | 10,320 | 10,320 | 10,320 | 6,272 | 6,272 | 6,272 |
| Embedded Memory (bits) | 423,936 | 423,936 | 423,936 | 270,336 | 270,336 | 270,336 |
| User I/Os | 88 | 88 | 88 | 88 | 88 | 88 |
| Speed Grade | 6 (faster) | 8 (slowest) | 7 | 6 (faster) | 8 (slowest) | 7 |
| Temperature Grade | Commercial (0C to +85C) | Commercial | Industrial (-40C to +85C) | Commercial | Commercial | Industrial |
| Parametric Match (vs target) | 100% | ~95% (slower speed grade) | ~95% (industrial temp) | ~80% (-39% logic, same package) | ~75% (less logic, slower speed) | ~75% (less logic, industrial temp) |
Key Differentiators
- Lowest static power in 144-LQFP Cyclone 10 LP family (vs 10CL006YE144C6G)
- Faster speed grade than the slowest Cyclone 10 LP variant (vs 10CL010YE144C8G)
- Commercial temperature grade optimized for cost-sensitive designs (vs 10CL010YE144A7G)
Design Notes
Estimated: the 144-LQFP exposed-pad package has a typical theta_JA of approximately 25 C/W with a 100 mm^2 copper pour on the EP, per the Cyclone 10 LP thermal model. At a typical 0.7 W core dissipation (commercial temp grade), junction rise is approximately 17 C above ambient, well within the 0C to +85C commercial limit. For designs pushing 1.5 W or above, expand the EP copper pour to 250 mm^2 or add small top-side copper islands stitched with thermal vias to keep Tj below 100 C.
Estimated: Cyclone 10 LP core current at 1.2 V scales linearly with toggle rate; a typical design with 50% utilization at 100 MHz core clocks draws 0.5 to 0.8 A on VCCINT and approximately 50 mA per active I/O bank on VCCIO. Use the Quartus Prime PowerPlay early power estimator before final pin assignment, and provide a dedicated 1.2 V LDO (such as a 1.5 A part) with at least 22 uF of bulk plus 0.1 uF high-frequency decoupling within 5 mm of each VCCINT pin group.
Estimated: place one 0.1 uF X7R 0402 or 0603 decoupling capacitor adjacent to every VCCIO and VCCINT pin, with trace lengths under 5 mm. Stitch the EP copper with at least 9 thermal vias (0.3 mm drill, 0.6 mm pad) arranged in a 3x3 array under the package, plated shut or tented to prevent solder wicking during reflow. Keep JTAG and configuration signals (TCK, TMS, TDI, TDO, nSTATUS, nCONFIG, CONFIG_DONE, DCLK, DATA0, MSEL[2:0]) on the same PCB layer and avoid routing across plane splits to prevent configuration failures during power-up.
Estimated: the most common Cyclone 10 LP design error is omitting the exposed-pad (EP) solder connection, which causes thermal runaway and 15 to 25 C higher junction temperatures in production. Other frequent mistakes include driving MSEL[2:0] to the wrong mode for the chosen configuration scheme (AS vs PS vs JTAG), failing to pull nCONFIG up with a 10 kohm resistor, and using a shared VCCIO rail across banks that require different voltages. Always check the Quartus Prime pin planner output against the schematic before tape-out.
Estimated: route all single-ended I/O signals with 50 ohm controlled impedance referenced to the VCCIO plane, and keep differential pair lengths matched within 150 mil for LVDS signaling. The 144-LQFP package has 0.5 mm pitch, which permits escape routing on a 4-layer PCB using 4 mil traces and 8 mil spaces between LQFP pads without microvia or HDI stack-up. Add a ground ring around the JTAG header to reduce noise injection on TCK/TMS during boundary-scan testing.
Compliance Information
Cyclone 10 LP family is RoHS compliant per Intel product documentation; halogen-free status not stated in provided web data. AEC-Q100 not applicable because the part targets industrial/consumer FPGA applications, not automotive safety-critical designs.
