10CL006YE144C8G - Cyclone 10 LP FPGA 6K LE EQFP-144 | Intel / Altera
MPN: 10CL006YE144C8G β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $65.43 | $65.43 |
| 10 | $58.89 | $588.90 |
| 100 | $52.34 | $5,234.00 |
| 500 | $46.8 | $23,400.00 |
| 1,000 | $41.25 | $41,250.00 |
Drop-in alternatives for 10CL006YE144C8G β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
10CL006YE144C6G
β Drop-Inβ In Stock
$8.15 / Unit
View Datasheet β10CL006YE144A7G
β Drop-Inβ In Stock
$17.4 / Unit
View Datasheet β10CL016YE144A7G
β Drop-Inβ In Stock
$27.95 / Unit
View Datasheet β10CL025YE144C8G
β Drop-Inπ Reference alternative (not in catalog)
10CL006YE144I7G
β Drop-Inβ In Stock
$11.2 / Unit
View Datasheet β10CL006YE144C8G Maximum Ratings & Electrical Characteristics
| Series | Cyclone 10 LP |
| Device Family | Cyclone 10 LP 10CL006 |
| Logic Elements (LE) | 6,272 |
| Logic Array Blocks (LAB) | 392 |
| Embedded Memory | 276,480 bits (270 kbit) |
| Embedded 18x18 Multipliers | 15 |
| PLLs | 4 |
| User I/O Count | 88 |
| Core Voltage | 1.2 V |
| Operating Temperature | 0C to +85C (commercial) |
| Grade Suffix | C8G (commercial, speed grade 8) |
| Package | 144-pin EQFP (EQFP-144) with exposed pad |
| Mounting Type | Surface Mount |
| MSL Level | 3 |
| Configuration Methods | Serial, JTAG, AS |
10CL006YE144C8G Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | GND β Ground |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | GND β Ground |
| Pin 11 | I/O β User I/O pin (bank 2) |
| Pin 12 | I/O β User I/O pin (bank 2) |
| Pin 13 | I/O β User I/O pin (bank 2) |
| Pin 14 | I/O β User I/O pin (bank 2) |
| Pin 15 | GND β Ground |
| Pin 16 | I/O β User I/O pin (bank 2) |
| Pin 17 | I/O β User I/O pin (bank 2) |
| Pin 18 | I/O β User I/O pin (bank 2) |
| Pin 19 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 20 | I/O β User I/O pin (bank 2) |
| Pin 21 | I/O β User I/O pin (bank 2) |
| Pin 22 | GND β Ground |
| Pin 23 | I/O β User I/O pin (bank 3) |
| Pin 24 | I/O β User I/O pin (bank 3) |
| Pin 25 | I/O β User I/O pin (bank 3) |
| Pin 26 | I/O β User I/O pin (bank 3) |
| Pin 27 | GND β Ground |
| Pin 28 | I/O β User I/O pin (bank 3) |
| Pin 29 | I/O β User I/O pin (bank 3) |
| Pin 30 | I/O β User I/O pin (bank 3) |
| Pin 31 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 32 | I/O β User I/O pin (bank 3) |
| Pin 33 | I/O β User I/O pin (bank 3) |
| Pin 34 | GND β Ground |
| Pin 35 | I/O β User I/O pin (bank 4) |
| Pin 36 | I/O β User I/O pin (bank 4) |
| Pin 37 | I/O β User I/O pin (bank 4) |
| Pin 38 | I/O β User I/O pin (bank 4) |
| Pin 39 | GND β Ground |
| Pin 40 | I/O β User I/O pin (bank 4) |
| Pin 41 | I/O β User I/O pin (bank 4) |
| Pin 42 | I/O β User I/O pin (bank 4) |
| Pin 43 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 44 | I/O β User I/O pin (bank 4) |
| Pin 45 | I/O β User I/O pin (bank 4) |
| Pin 46 | GND β Ground |
| Pin 47 | I/O β User I/O pin (bank 5) |
| Pin 48 | I/O β User I/O pin (bank 5) |
| Pin 49 | I/O β User I/O pin (bank 5) |
| Pin 50 | I/O β User I/O pin (bank 5) |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β User I/O pin (bank 5) |
| Pin 53 | I/O β User I/O pin (bank 5) |
| Pin 54 | I/O β User I/O pin (bank 5) |
| Pin 55 | VCCIO5 β I/O bank 5 supply voltage |
| Pin 56 | I/O β User I/O pin (bank 5) |
| Pin 57 | I/O β User I/O pin (bank 5) |
| Pin 58 | GND β Ground |
| Pin 59 | I/O β User I/O pin (bank 6) |
| Pin 60 | I/O β User I/O pin (bank 6) |
| Pin 61 | I/O β User I/O pin (bank 6) |
| Pin 62 | I/O β User I/O pin (bank 6) |
| Pin 63 | GND β Ground |
| Pin 64 | I/O β User I/O pin (bank 6) |
| Pin 65 | I/O β User I/O pin (bank 6) |
| Pin 66 | I/O β User I/O pin (bank 6) |
| Pin 67 | VCCIO6 β I/O bank 6 supply voltage |
| Pin 68 | I/O β User I/O pin (bank 6) |
| Pin 69 | I/O β User I/O pin (bank 6) |
| Pin 70 | GND β Ground |
| Pin 71 | I/O β User I/O pin (bank 7) |
| Pin 72 | I/O β User I/O pin (bank 7) |
| Pin 73 | I/O β User I/O pin (bank 7) |
| Pin 74 | I/O β User I/O pin (bank 7) |
| Pin 75 | GND β Ground |
| Pin 76 | I/O β User I/O pin (bank 7) |
| Pin 77 | I/O β User I/O pin (bank 7) |
| Pin 78 | I/O β User I/O pin (bank 7) |
| Pin 79 | VCCIO7 β I/O bank 7 supply voltage |
| Pin 80 | I/O β User I/O pin (bank 7) |
| Pin 81 | I/O β User I/O pin (bank 7) |
| Pin 82 | GND β Ground |
| Pin 83 | I/O β User I/O pin (bank 8) |
| Pin 84 | I/O β User I/O pin (bank 8) |
| Pin 85 | I/O β User I/O pin (bank 8) |
| Pin 86 | I/O β User I/O pin (bank 8) |
| Pin 87 | GND β Ground |
| Pin 88 | I/O β User I/O pin (bank 8) |
| Pin 89 | I/O β User I/O pin (bank 8) |
| Pin 90 | I/O β User I/O pin (bank 8) |
| Pin 91 | VCCIO8 β I/O bank 8 supply voltage |
| Pin 92 | I/O β User I/O pin (bank 8) |
| Pin 93 | I/O β User I/O pin (bank 8) |
| Pin 94 | GND β Ground |
| Pin 95 | TMS β JTAG test mode select |
| Pin 96 | TCK β JTAG test clock |
| Pin 97 | TDI β JTAG test data in |
| Pin 98 | nCONFIG β Configuration start (active low) |
| Pin 99 | nSTATUS β Configuration status (active low) |
| Pin 100 | CONF_DONE β Configuration done |
| Pin 101 | MSEL0 β Configuration mode select 0 |
| Pin 102 | MSEL1 β Configuration mode select 1 |
| Pin 103 | MSEL2 β Configuration mode select 2 |
| Pin 104 | nCE β Chip enable (active low) |
| Pin 105 | TDO β JTAG test data out |
| Pin 106 | CLK0 β Dedicated clock input 0 |
| Pin 107 | CLK1 β Dedicated clock input 1 |
| Pin 108 | CLK2 β Dedicated clock input 2 |
| Pin 109 | CLK3 β Dedicated clock input 3 |
| Pin 110 | VCCINT β Core supply voltage (1.2 V) |
| Pin 111 | VCCINT β Core supply voltage (1.2 V) |
| Pin 112 | GND β Ground |
| Pin 113 | VCCA_PLL1 β PLL1 analog supply |
| Pin 114 | GNDA_PLL1 β PLL1 analog ground |
| Pin 115 | VCCA_PLL2 β PLL2 analog supply |
| Pin 116 | GNDA_PLL2 β PLL2 analog ground |
| Pin 117 | VCCA_PLL3 β PLL3 analog supply |
| Pin 118 | GNDA_PLL3 β PLL3 analog ground |
| Pin 119 | VCCA_PLL4 β PLL4 analog supply |
| Pin 120 | GNDA_PLL4 β PLL4 analog ground |
| Pin 121 | VCCPD β Pre-driver supply voltage |
| Pin 122 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 123 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 124 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 125 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 126 | VCCIO5 β I/O bank 5 supply voltage |
| Pin 127 | VCCIO6 β I/O bank 6 supply voltage |
| Pin 128 | VCCIO7 β I/O bank 7 supply voltage |
| Pin 129 | VCCIO8 β I/O bank 8 supply voltage |
| Pin 130 | GND β Ground |
| Pin 131 | DATA0 β Configuration data 0 (AS mode) |
| Pin 132 | DCLK β Configuration clock (AS mode) |
| Pin 133 | nCSO β Chip select out (AS mode) |
| Pin 134 | ASDO β Active serial data out |
| Pin 135 | I/O β User I/O pin (bank 1) |
| Pin 136 | I/O β User I/O pin (bank 1) |
| Pin 137 | I/O β User I/O pin (bank 2) |
| Pin 138 | I/O β User I/O pin (bank 2) |
| Pin 139 | I/O β User I/O pin (bank 3) |
| Pin 140 | I/O β User I/O pin (bank 3) |
| Pin 141 | I/O β User I/O pin (bank 4) |
| Pin 142 | I/O β User I/O pin (bank 4) |
| Pin 143 | I/O β User I/O pin (bank 5) |
| Pin 144 | EP β Exposed pad (thermal pad, must be soldered to PCB ground) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CL006YE144C8G is suitable for 6 applications: Industrial Motor Control, Video Bridging and Display Controllers, Low-Cost Protocol Bridging, Portable Medical Device Glue Logic, IoT Edge Nodes, Test and Measurement Instrumentation.
Industrial Motor Control
The 10CL006YE144C8G suits industrial motor-control applications with its 88 user I/O count for encoder, Hall-sensor, and PWM interfaces, four PLLs for precise switching-frequency synthesis, and 15 embedded 18x18 multipliers for field-oriented control (FOC) math. Operating from 0C to +85C junction, the device fits benign industrial enclosures; designers should migrate to the I-suffix variant for -40C operation. The 6,272 logic elements and 270 kbit of embedded memory provide ample headroom for torque-ripple minimization and adaptive control algorithms. Integrated JTAG and serial configuration simplify in-field firmware updates for deployed motor drives.
Recommended
Video Bridging and Display Controllers
The 10CL006YE144C8G is a cost-effective bridge controller for converting parallel CMOS camera data to MIPI CSI-2, LVDS, or HDMI, using the embedded multipliers for color-space conversion and scaling. Its 88 user I/O accommodate parallel RGB or BT.656 input alongside I2C control channels, while 270 kbit of embedded memory buffer line-rate data without external SRAM. The 1.2 V core minimizes power in always-on kiosk and signage displays. Designers can leverage the Altera Video and Image Processing (VIP) suite within Quartus Prime to accelerate development of de-interlacing and resolution-conversion pipelines.
Recommended
Low-Cost Protocol Bridging
The 10CL006YE144C8G excels as a multi-protocol bridge, mapping UART, SPI, I2C, GPIO, and PWM buses between heterogeneous MCUs, sensors, and host processors. With 88 I/O available, the device can fan out to multiple peripheral domains simultaneously, while the four PLLs generate independent clock domains for each interface. The Cyclone 10 LP's low static power reduces idle drain in always-on bridging applications. The device's JTAG and serial configuration interfaces enable in-field protocol-stack updates without physical board access, a major advantage for IoT gateway deployments.
Recommended
Portable Medical Device Glue Logic
The 10CL006YE144C8G serves as low-power glue logic in portable medical devices such as blood-glucose meters, pulse-oximeters, and handheld ultrasound probes. The Cyclone 10 LP's low static power extends battery runtime, while the 88 I/O count and 270 kbit of embedded memory support integration of multiple sensor frontends, audio codecs, and TFT displays. The 1.2 V core voltage simplifies power-tree design in 1-cell Li-ion or 2xAA battery topologies. Designers should pair the FPGA with the industrial-grade 'I' suffix variant for medical environments requiring -40C operation.
Recommended
IoT Edge Nodes
The 10CL006YE144C8G is well suited to IoT edge nodes performing local sensor aggregation, anomaly detection, and protocol conversion before forwarding data over Ethernet, Wi-Fi, or LoRa. The 6,272 logic elements and 15 embedded multipliers enable lightweight ML inference and signal preprocessing at the edge, while the four PLLs synthesize clocks for Ethernet PHYs and radio transceivers. The device's low static power and 0C to +85C commercial range support indoor and sheltered-outdoor installations. Quartus Prime Lite allows low-cost development for prototypes and low-volume products.
Recommended
Test and Measurement Instrumentation
The 10CL006YE144C8G integrates into low-channel-count test instruments such as protocol analyzers, logic-level translators, and benchtop data-acquisition frontends. The 88 user I/O count supports multi-channel stimulus/response, while the 15 embedded 18x18 multipliers accelerate FFT and DSP-based measurements. The 270 kbit of embedded memory captures trace buffers for protocol decoding. JTAG-based configuration enables rapid firmware iteration during instrument development, and the commercial 0C to +85C range is appropriate for laboratory environments.
Recommended
Recommended Products Summary
Engineering reference data for 10CL006YE144C8G β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CL006YE144C6G | 10CL006YE144A7G | 10CL016YE144A7G | 10CL025YE144C8G | 10CL006YE144I7G |
|---|---|---|---|---|---|---|
| Brand | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel | Altera / Intel |
| Package | EQFP-144 | EQFP-144 - same | EQFP-144 - same | EQFP-144 - same | EQFP-144 - same | EQFP-144 - same |
| Logic Elements (LE) | 6,272 | 6,272 | 6,272 | 15,408 (+145%) | 24,624 (+292%) | 6,272 |
| Embedded Memory | 270 kbit | 270 kbit | 270 kbit | 504 kbit | 594 kbit | 270 kbit |
| Embedded 18x18 Multipliers | 15 | 15 | 15 | 45 | 66 | 15 |
| PLLs | 4 | 4 | 4 | 4 | 4 | 4 |
| User I/O Count | 88 | 88 | 88 | 88 | 88 | 88 |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C (commercial) | -40C to +100C (industrial) | -40C to +100C (industrial) | 0C to +85C (commercial) | -40C to +100C (industrial) |
| Speed Grade | 8 | 6 (slower) | 7 | 7 | 8 (same) | 7 |
| Core Voltage | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
Key Differentiators
- Higher logic-element density in the same footprint (vs 10CL006YE144C6G (same 6,272 LE but slower speed grade 6))
- Commercial temperature grade for cost-sensitive applications (vs 10CL006YE144A7G (industrial -40C to +100C))
- Direct in-place upgrade path to higher density (vs 10CL016YE144A7G and 10CL025YE144C8G (15,408 and 24,624 LE))
- Lowest static power in the Cyclone 10 LP family (vs Cyclone IV E EP4CE6E22C8G (predecessor))
Design Notes
The 10CL006YE144C8G requires a regulated 1.2 V core supply (VCCINT) plus a 2.5 V/3.3 V pre-driver supply (VCCPD) and per-bank VCCIO supplies. Decouple VCCINT with at least one 10 uF bulk capacitor and several 0.1 uF/1 uF ceramic capacitors placed within 3 mm of each VCCINT pin. The four PLL analog supplies (VCCA_PLL1..4) require their own filtered analog rails to minimize jitter; isolate them from digital VCCINT with a ferrite bead or pi-filter. Bank VCCIO supplies can be independently set to 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V per the Cyclone 10 LP handbook.
The EQFP-144 package exposes a thermal pad (pin 144 / EP) that must be soldered to a PCB ground plane for heat dissipation. Estimated: with the EP connected to approximately 1 sq inch of 1 oz copper inner plane, the junction-to-ambient thermal resistance (theta_JA) is approximately 25-30 C/W. Cyclone 10 LP static power is typically below 100 mW for the 10CL006; dynamic power scales with toggle rate and should be estimated using the Quartus Prime PowerPlay Analyzer before committing to volume. For enclosed industrial enclosures without forced airflow, verify junction temperature via PowerPlay thermal analysis.
Route all eight bank VCCIO supplies with wide traces or power planes to minimize IR drop. Place MSEL pull-up/pull-down resistors as close to the package as possible to set the correct configuration mode (AS fast/standard, JTAG, PS). Series-damp all eight CLK dedicated clock inputs with 33 ohm resistors if the source clock is longer than 25 mm or has fast edges. Keep JTAG signals away from switching I/O to avoid noise coupling during configuration.
Do not leave MSEL pins floating - the configuration mode is undefined and the device may not boot. Do not tie nCONFIG directly to VCC without a button or supervisor - this prevents the device from re-entering configuration. Avoid driving user I/O before configuration completes (before CONF_DONE rises); this can cause high-current latch-up. When migrating from Cyclone IV to Cyclone 10 LP, do NOT reuse pinout files - the Cyclone 10 LP EQFP-144 pinout is not pin-compatible with the Cyclone IV EQFP-144 footprint.
Match-impedance control on high-speed differential pairs is critical for LVDS and DDR memory interfaces. For DDR3 SDRAM interfaces, use 50 ohm single-ended trace impedance with matched pair length within 50 mils. For LVDS outputs, route 100 ohm differential pairs and avoid 90-degree bends. Use the Quartus Prime TimeQuest timing analyzer to verify timing closure before board layout sign-off, especially for designs crossing clock domains between the four PLLs.
Compliance Information
RoHS compliant per Altera/Intel product page. Commercial temperature grade (0C to +85C); not AEC-Q100 qualified. Choose the 10CL006YE144A7G or 10CL006YE144I7G variants for industrial or automotive-grade applications.
