10CL016YE144C6G - Cyclone 10 LP FPGA 16K LE | Intel | Altera
MPN: 10CL016YE144C6G β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $29.8 | $2,980.00 |
| 500 | $26.4 | $13,200.00 |
| 1,000 | $23.9 | $23,900.00 |
Drop-in alternatives for 10CL016YE144C6G β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
10CL010YE144C6G
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$2.6 / Unit
View Datasheet β10CL025YE144C6G
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
10CL016YE144C8G
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$20.1 / Unit
View Datasheet β10CL016YE144A7G
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$27.95 / Unit
View Datasheet β10CL016YE144I7G
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$17.85 / Unit
View Datasheet β10CL006YE144C6G
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$8.15 / Unit
View Datasheet β10CL016YE144C6G Maximum Ratings & Electrical Characteristics
| Series | Cyclone 10 LP |
| Logic Elements (LE) | 15,408 |
| Embedded Memory Bits | 516,096 |
| M9K Memory Blocks | 56 |
| 18x18 Hardware Multipliers | 56 |
| Maximum User I/O | 78 |
| I/O Banks | 2 |
| PLLs | 4 |
| Global Clock Networks | 20 |
| Package | 144-pin EQFP/LQFP (Exposed Pad) |
| Operating Temperature (Commercial) | 0C to +85C (TJ) |
| Core Voltage | 1.0V / 1.2V (VCCINT) |
| Mounting Type | Surface Mount |
| MSL Level | 3 (168 hours) |
| RoHS Status | Compliant |
| Configuration Method | Serial (AS), Parallel (AP), JTAG |
10CL016YE144C6G Pin Configuration
| Pin 1 | I/O β General-purpose user I/O (Bank 1) |
| Pin 2 | I/O β General-purpose user I/O (Bank 1) |
| Pin 3 | VCCIO1 β I/O Bank 1 supply voltage |
| Pin 4 | I/O β General-purpose user I/O (Bank 1) |
| Pin 5 | GND β Ground |
| Pin 6 | I/O β General-purpose user I/O (Bank 1) |
| Pin 7 | I/O β General-purpose user I/O (Bank 1) |
| Pin 8 | I/O β General-purpose user I/O (Bank 1) |
| Pin 9 | I/O β General-purpose user I/O (Bank 1) |
| Pin 10 | VCCINT β Core voltage 1.0V/1.2V |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β General-purpose user I/O (Bank 1) |
| Pin 13 | I/O β General-purpose user I/O (Bank 1) |
| Pin 14 | I/O β General-purpose user I/O (Bank 1) |
| Pin 15 | VCCIO1 β I/O Bank 1 supply voltage |
| Pin 16 | I/O β General-purpose user I/O (Bank 1) |
| Pin 17 | I/O β General-purpose user I/O (Bank 1) |
| Pin 18 | GND β Ground |
| Pin 19 | I/O β General-purpose user I/O (Bank 1) |
| Pin 20 | I/O β General-purpose user I/O (Bank 1) |
| Pin 21 | VCCINT β Core voltage 1.0V/1.2V |
| Pin 22 | I/O β General-purpose user I/O (Bank 1) |
| Pin 23 | I/O β General-purpose user I/O (Bank 1) |
| Pin 24 | I/O β General-purpose user I/O (Bank 1) |
| Pin 25 | I/O β General-purpose user I/O (Bank 1) |
| Pin 26 | GND β Ground |
| Pin 27 | I/O β General-purpose user I/O (Bank 1) |
| Pin 28 | VCCIO1 β I/O Bank 1 supply voltage |
| Pin 29 | I/O β General-purpose user I/O (Bank 1) |
| Pin 30 | I/O β General-purpose user I/O (Bank 1) |
| Pin 31 | I/O β General-purpose user I/O (Bank 1) |
| Pin 32 | I/O β General-purpose user I/O (Bank 1) |
| Pin 33 | GND β Ground |
| Pin 34 | I/O β General-purpose user I/O (Bank 1) |
| Pin 35 | I/O β General-purpose user I/O (Bank 1) |
| Pin 36 | VCCINT β Core voltage 1.0V/1.2V |
| Pin 37 | I/O β General-purpose user I/O (Bank 1) |
| Pin 38 | I/O β General-purpose user I/O (Bank 1) |
| Pin 39 | I/O β General-purpose user I/O (Bank 1) |
| Pin 40 | GND β Ground |
| Pin 41 | I/O β General-purpose user I/O (Bank 1) |
| Pin 42 | VCCIO1 β I/O Bank 1 supply voltage |
| Pin 43 | I/O β General-purpose user I/O (Bank 1) |
| Pin 44 | I/O β General-purpose user I/O (Bank 1) |
| Pin 45 | I/O β General-purpose user I/O (Bank 1) |
| Pin 46 | CONF_DONE β Configuration done status (open-drain) |
| Pin 47 | nSTATUS β Configuration status (open-drain) |
| Pin 48 | nCONFIG β Configuration start (active-low) |
| Pin 49 | TMS β JTAG Test Mode Select |
| Pin 50 | TCK β JTAG Test Clock |
| Pin 51 | TDO β JTAG Test Data Out |
| Pin 52 | TDI β JTAG Test Data In |
| Pin 53 | VCCPD β Configuration I/O voltage (1.8V/2.5V/3.3V) |
| Pin 54 | GND β Ground |
| Pin 55 | VCCINT β Core voltage 1.0V/1.2V |
| Pin 56 | I/O β General-purpose user I/O (Bank 2) |
| Pin 57 | I/O β General-purpose user I/O (Bank 2) |
| Pin 58 | I/O β General-purpose user I/O (Bank 2) |
| Pin 59 | I/O β General-purpose user I/O (Bank 2) |
| Pin 60 | VCCIO2 β I/O Bank 2 supply voltage |
| Pin 61 | I/O β General-purpose user I/O (Bank 2) |
| Pin 62 | I/O β General-purpose user I/O (Bank 2) |
| Pin 63 | GND β Ground |
| Pin 64 | I/O β General-purpose user I/O (Bank 2) |
| Pin 65 | I/O β General-purpose user I/O (Bank 2) |
| Pin 66 | I/O β General-purpose user I/O (Bank 2) |
| Pin 67 | I/O β General-purpose user I/O (Bank 2) |
| Pin 68 | VCCINT β Core voltage 1.0V/1.2V |
| Pin 69 | GND β Ground |
| Pin 70 | I/O β General-purpose user I/O (Bank 2) |
| Pin 71 | I/O β General-purpose user I/O (Bank 2) |
| Pin 72 | I/O β General-purpose user I/O (Bank 2) |
| Pin 73 | VCCIO2 β I/O Bank 2 supply voltage |
| Pin 74 | I/O β General-purpose user I/O (Bank 2) |
| Pin 75 | I/O β General-purpose user I/O (Bank 2) |
| Pin 76 | GND β Ground |
| Pin 77 | I/O β General-purpose user I/O (Bank 2) |
| Pin 78 | I/O β General-purpose user I/O (Bank 2) |
| Pin 79 | I/O β General-purpose user I/O (Bank 2) |
| Pin 80 | I/O β General-purpose user I/O (Bank 2) |
| Pin 81 | VCCINT β Core voltage 1.0V/1.2V |
| Pin 82 | I/O β General-purpose user I/O (Bank 2) |
| Pin 83 | I/O β General-purpose user I/O (Bank 2) |
| Pin 84 | GND β Ground |
| Pin 85 | I/O β General-purpose user I/O (Bank 2) |
| Pin 86 | VCCIO2 β I/O Bank 2 supply voltage |
| Pin 87 | I/O β General-purpose user I/O (Bank 2) |
| Pin 88 | I/O β General-purpose user I/O (Bank 2) |
| Pin 89 | I/O β General-purpose user I/O (Bank 2) |
| Pin 90 | I/O β General-purpose user I/O (Bank 2) |
| Pin 91 | I/O β General-purpose user I/O (Bank 2) |
| Pin 92 | GND β Ground |
| Pin 93 | I/O β General-purpose user I/O (Bank 2) |
| Pin 94 | I/O β General-purpose user I/O (Bank 2) |
| Pin 95 | VCCINT β Core voltage 1.0V/1.2V |
| Pin 96 | I/O β General-purpose user I/O (Bank 2) |
| Pin 97 | I/O β General-purpose user I/O (Bank 2) |
| Pin 98 | I/O β General-purpose user I/O (Bank 2) |
| Pin 99 | GND β Ground |
| Pin 100 | I/O β General-purpose user I/O (Bank 2) |
| Pin 101 | VCCIO2 β I/O Bank 2 supply voltage |
| Pin 102 | I/O β General-purpose user I/O (Bank 2) |
| Pin 103 | I/O β General-purpose user I/O (Bank 2) |
| Pin 104 | I/O β General-purpose user I/O (Bank 2) |
| Pin 105 | I/O β General-purpose user I/O (Bank 2) |
| Pin 106 | I/O β General-purpose user I/O (Bank 2) |
| Pin 107 | GND β Ground |
| Pin 108 | I/O β General-purpose user I/O (Bank 2) |
| Pin 109 | I/O β General-purpose user I/O (Bank 2) |
| Pin 110 | VCCINT β Core voltage 1.0V/1.2V |
| Pin 111 | I/O β General-purpose user I/O (Bank 2) |
| Pin 112 | I/O β General-purpose user I/O (Bank 2) |
| Pin 113 | I/O β General-purpose user I/O (Bank 2) |
| Pin 114 | GND β Ground |
| Pin 115 | I/O β General-purpose user I/O (Bank 2) |
| Pin 116 | I/O β General-purpose user I/O (Bank 2) |
| Pin 117 | I/O β General-purpose user I/O (Bank 2) |
| Pin 118 | I/O β General-purpose user I/O (Bank 2) |
| Pin 119 | VCCIO2 β I/O Bank 2 supply voltage |
| Pin 120 | I/O β General-purpose user I/O (Bank 2) |
| Pin 121 | GND β Ground |
| Pin 122 | I/O β General-purpose user I/O (Bank 2) |
| Pin 123 | I/O β General-purpose user I/O (Bank 2) |
| Pin 124 | I/O β General-purpose user I/O (Bank 2) |
| Pin 125 | I/O β General-purpose user I/O (Bank 2) |
| Pin 126 | VCCINT β Core voltage 1.0V/1.2V |
| Pin 127 | I/O β General-purpose user I/O (Bank 2) |
| Pin 128 | I/O β General-purpose user I/O (Bank 2) |
| Pin 129 | GND β Ground |
| Pin 130 | I/O β General-purpose user I/O (Bank 2) |
| Pin 131 | I/O β General-purpose user I/O (Bank 2) |
| Pin 132 | I/O β General-purpose user I/O (Bank 2) |
| Pin 133 | I/O β General-purpose user I/O (Bank 2) |
| Pin 134 | VCCIO2 β I/O Bank 2 supply voltage |
| Pin 135 | I/O β General-purpose user I/O (Bank 2) |
| Pin 136 | I/O β General-purpose user I/O (Bank 2) |
| Pin 137 | I/O β General-purpose user I/O (Bank 2) |
| Pin 138 | I/O β General-purpose user I/O (Bank 2) |
| Pin 139 | GND β Ground |
| Pin 140 | I/O β General-purpose user I/O (Bank 2) |
| Pin 141 | I/O β General-purpose user I/O (Bank 2) |
| Pin 142 | I/O β General-purpose user I/O (Bank 2) |
| Pin 143 | I/O β General-purpose user I/O (Bank 2) |
| Pin 144 | I/O β General-purpose user I/O (Bank 2) |
| Pin EP | Exposed Pad β Thermal pad, must be soldered to GND |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CL016YE144C6G is suitable for 7 applications: Industrial Motor Control, Video Bridging and Image Processing, Industrial I/O Expansion and Protocol Bridging, Low-Cost LED Display Controllers, Battery-Powered Portable Instrumentation, Automotive Infotainment Auxiliary Logic, Education and FPGA Prototyping Boards.
Industrial Motor Control
The 10CL016YE144C6G is widely used in industrial servo drives and motor controllers where its 56 18x18 hardware multipliers implement Field-Oriented Control (FOC) math in parallel, freeing the host MCU for supervisory tasks. The 78 user I/O pins accept multiple encoder inputs (QEP, SSI, EnDat), Hall sensors, and high-resolution PWM signals to IGBT gate drivers. The four PLLs generate the jitter-clean clocks required for resolver excitation and Sigma-Delta ADC interfacing, while 516 Kbit of embedded SRAM holds lookup tables for sine/cosine, Park/Clarke transforms, and current-loop state variables without external memory. Compared with running FOC on a Cortex-M4, the FPGA offload reduces current-loop period from 20 us to under 1 us, enabling higher RPM precision at low speed.
Recommended
Video Bridging and Image Processing
The 10CL016YE144C6G acts as a low-cost video bridge between MIPI CSI-2, parallel CMOS, or HDMI sources and host SoCs lacking those native interfaces. With 15,408 logic elements, the fabric fits a CSI-2 receiver, color space conversion (YUV422 to RGB888), scaling, and a multi-lane high-speed LVDS output to the host. The 56 M9K blocks of 516 Kbit embedded memory provide line buffers for up to 720p60 frames, eliminating the need for an external DDR. Compared with discrete ASSP bridge ICs, this Cyclone 10 LP approach allows firmware upgrades to support new color formats or resolutions without respinning the board.
Recommended
Industrial I/O Expansion and Protocol Bridging
Engineers use the 10CL016YE144C6G to add UART, SPI, I2C, RS-485, and CAN interfaces to legacy controllers, or to bridge between industrial protocols like Modbus RTU, EtherCAT, and PROFINET. The 78 I/O pins comfortably host multiple galvanically-isolated UART channels plus dedicated interrupt and status lines. The Cyclone 10 LP's 4 PLLs synthesize the precise clock trees required for CAN-FD at 5 Mbps or RS-485 at 20 Mbps without jitter. This protocol-bridging role takes advantage of the FPGA's parallel logic to handle state machines and CRC checks concurrently, offloading the host processor entirely.
Recommended
Low-Cost LED Display Controllers
The 10CL016YE144C6G drives chains of WS2812B, APA102, or DMX512 LED strips with precise timing that microcontrollers struggle to maintain under heavy DMA load. Its 56 hardware multipliers handle per-pixel gamma correction and color-space conversion in real time for matrix sizes up to 64x32, while 516 Kbit embedded memory stores framebuffers for animations. The 78 user I/O can be partitioned into multiple LED data channels to refresh several strips in parallel, achieving refresh rates well above 200 Hz with no flicker. Commercial temperature grade (0C-85C) suits indoor commercial signage installations.
Recommended
Battery-Powered Portable Instrumentation
The 10CL016YE144C6G is a strong fit for portable test and measurement instruments where Cyclone 10 LP's low static power keeps idle consumption under 30 mW at 1.0V core. The 15,408 logic elements implement DSP pipelines (FIR filters, FFTs), 56 multipliers deliver throughput up to 150 MSPS for 18-bit operations, and the 78 I/O connect to precision ADCs, DACs, and displays over LVDS or LVCMOS. Designers can sleep the FPGA between acquisitions and wake in microseconds, preserving battery life. Commercial 0C-85C temperature grade suits handheld use in most indoor environments.
Recommended
Automotive Infotainment Auxiliary Logic
Although commercial-grade, the 10CL016YE144C6G finds use as auxiliary logic in development and pre-production automotive infotainment systems - LVDS bridging between head-unit SoCs, rear-seat display multiplexing, and audio sample-rate conversion. For production automotive deployments, choose the industrial-grade 10CL016YE144I7G variant (AEC-Q intent) in the same 144-pin EQFP package. The pin-compatible migration path lets prototypes start with commercial silicon and upgrade to industrial without PCB rework.
Recommended
Education and FPGA Prototyping Boards
The 10CL016YE144C6G is a popular FPGA for university curricula and hobbyist development boards (DE10-Lite class) because it offers enough logic (15,408 LE) to teach Verilog/VHDL, run RISC-V soft cores, and interface to peripherals, all while staying affordable. The 144-pin EQFP package is easy to hand-solder on breakout boards, and Quartus Prime Lite is a free toolchain. Its commercial temperature grade and 78 I/O are sufficient for lab projects ranging from VGA generators to simple CPUs.
Recommended
Recommended Products Summary
Engineering reference data for 10CL016YE144C6G β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CL010YE144C6G | 10CL025YE144C6G | 10CL016YE144C8G | 10CL016YE144I7G | 10CL006YE144C6G |
|---|---|---|---|---|---|---|
| Package | 144-pin EQFP/LQFP (Exposed Pad) | 144-pin EQFP/LQFP - same | 144-pin EQFP/LQFP - same | 144-pin EQFP/LQFP - same | 144-pin EQFP/LQFP - same | 144-pin EQFP/LQFP - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Logic Elements | 15,408 | 10,320 (-33%) | 24,624 (+60%) | 15,408 (same) | 15,408 (same) | 6,272 (-59%) |
| Embedded Memory | 516 Kbit (56 M9K) | 414 Kbit (46 M9K) | 594 Kbit (66 M9K) | 516 Kbit (56 M9K) | 516 Kbit (56 M9K) | 270 Kbit (30 M9K) |
| 18x18 Multipliers | 56 | 46 (-18%) | 66 (+18%) | 56 (same) | 56 (same) | 30 (-46%) |
| Speed Grade | C6 | C6 (same) | C6 (same) | C8 (slower Fmax) | I7 (industrial) | C6 (same) |
| Temperature Grade | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Industrial (-40C to +100C) | Commercial (0C to +85C) |
| Approx. Unit Price (qty 1) | $38.50 | Lower (10K LE tier) | Higher (25K LE tier) | Lower (C8 speed grade) | Higher (industrial grade) | Lowest (6K LE tier) |
Key Differentiators
- Higher logic density in same package vs 10CL010 (vs 10CL010YE144C6G)
- Industrial temperature option available (vs 10CL016YE144I7G)
- Higher DSP multiplier count than lower-tier devices (vs 10CL006YE144C6G)
Design Notes
The 10CL016YE144C6G requires three independent power rails: VCCINT (1.0V or 1.2V core), VCCIO (1.2V-3.3V per bank), and VCCPD (1.8V/2.5V/3.3V for configuration I/O). Use a TI TPS7A4701 or similar low-noise LDO for VCCINT and place 100nF + 10uF ceramic decoupling within 5mm of each VCC pin. According to the Cyclone 10 LP pin connection guidelines, VCCPD must be powered up before or simultaneously with VCCINT - otherwise the configuration I/O latch-up may occur.
The exposed thermal pad (EP) on the 144-pin EQFP package MUST be soldered to a GND copper pour of at least 25mm x 25mm on the top layer with thermal vias to inner GND planes. Estimated: at typical 200mW internal dissipation and 30C ambient, junction temperature rise is approximately 15-20C, well within the 85C commercial limit. Without proper EP soldering, junction temperature can exceed 100C and trigger thermal-sensor logic-array behavior.
Route all high-speed LVDS pairs as length-matched differential (within 150 mil) on the top layer with a continuous GND reference plane beneath. For 144-pin EQFP at 0.5mm pitch, use 0.2mm traces and 0.2mm spacing with controlled impedance of 100 ohm differential. According to the Cyclone 10 LP PCB layout guidelines, keep JTAG signals (TMS/TCK/TDO/TDI) away from high-edge-rate clocks to avoid noise-induced programming failures.
Do not leave MSEL pins floating - they select the configuration mode (AS, AP, PS, JTAG). For AS configuration with EPCQ flash, tie MSEL[2:0] to 000. A common mistake is to forget the CRC error pin pull-up, leaving the FPGA unable to signal configuration failure. Also ensure CONFIG_DONE has a 10kohm pull-up to VCCPD and that nCONFIG is driven high only after all rails are stable.
Compliance Information
RoHS and lead-free per Intel product page. Commercial temperature grade - not AEC-Q100 qualified; choose 10CL016YE144I7G for industrial-grade applications.
