10CL025YE144C6G - Cyclone 10 LP FPGA, 25K LE, 144-EQFP | Intel
MPN: 10CL025YE144C6G ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $32.97 | $32.97 |
| 10 | $30.52 | $305.20 |
| 100 | $26.42 | $2,642.00 |
| 500 | $23.71 | $11,855.00 |
| 1,000 | $21.89 | $21,890.00 |
Drop-in alternatives for 10CL025YE144C6G — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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10CL025YE144I7G
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$35.8 / Unit
View Datasheet →10CL025YE144C8G
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$36.85 / Unit
View Datasheet →10CL025YE144A7G
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$6.3 / Unit
View Datasheet →10CL016YE144C6G
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$23.9 / Unit
View Datasheet →10CL010YE144C6G
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$2.6 / Unit
View Datasheet →10CL006YE144C6G
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$8.15 / Unit
View Datasheet →10CL025YE144C6G Maximum Ratings & Electrical Characteristics
| Series | Cyclone 10 LP |
| Family | Cyclone 10 LP Field Programmable Gate Array |
| Logic Elements (LEs) | 24,624 |
| Embedded Memory (bits) | 608,256 |
| Memory Blocks | M9K blocks, 76 total |
| 18x18 Hardware Multipliers | 156 |
| User I/O Count | 76 |
| Logic Array Blocks (LABs) | 1,539 |
| PLLs | 4 |
| Global Clocks | 20 |
| Core Voltage | 1.0 V (typical) |
| Process Node | 60 nm low-power CMOS |
| Speed Grade | 6 (fastest commercial) |
| Operating Temperature | 0C to +85C (commercial) |
| Package | 144-LQFP Exposed Pad (EQFP-144), 22x22 mm |
| Mounting Type | Surface Mount |
| Lead-Free / RoHS | Compliant |
| Configuration Scheme | SRAM-based, via JTAG / Active Serial / Active Parallel |
10CL025YE144C6G Pin Configuration
| Pin 1 | I/O — General-purpose user I/O bank 1 |
| Pin 2 | I/O — General-purpose user I/O bank 1 |
| Pin 3 | I/O — General-purpose user I/O bank 1 |
| Pin 4 | I/O — General-purpose user I/O bank 1 |
| Pin 5 | I/O — General-purpose user I/O bank 1 |
| Pin 6 | I/O — General-purpose user I/O bank 1 |
| Pin 7 | I/O — General-purpose user I/O bank 1 |
| Pin 8 | I/O — General-purpose user I/O bank 1 |
| Pin 9 | I/O — General-purpose user I/O bank 1 |
| Pin 10 | I/O — General-purpose user I/O bank 1 |
| Pin 11 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 12 | I/O — General-purpose user I/O bank 1 |
| Pin 13 | I/O — General-purpose user I/O bank 1 |
| Pin 14 | I/O — General-purpose user I/O bank 1 |
| Pin 15 | I/O — General-purpose user I/O bank 1 |
| Pin 16 | I/O — General-purpose user I/O bank 1 |
| Pin 17 | I/O — General-purpose user I/O bank 1 |
| Pin 18 | I/O — General-purpose user I/O bank 1 |
| Pin 19 | I/O — General-purpose user I/O bank 1 |
| Pin 20 | I/O — General-purpose user I/O bank 1 |
| Pin 21 | VCCINT — Core supply voltage (1.0 V typical) |
| Pin 22 | GND — Ground |
| Pin 23 | I/O — General-purpose user I/O bank 2 |
| Pin 24 | I/O — General-purpose user I/O bank 2 |
| Pin 25 | I/O — General-purpose user I/O bank 2 |
| Pin 26 | I/O — General-purpose user I/O bank 2 |
| Pin 27 | I/O — General-purpose user I/O bank 2 |
| Pin 28 | I/O — General-purpose user I/O bank 2 |
| Pin 29 | I/O — General-purpose user I/O bank 2 |
| Pin 30 | I/O — General-purpose user I/O bank 2 |
| Pin 31 | I/O — General-purpose user I/O bank 2 |
| Pin 32 | I/O — General-purpose user I/O bank 2 |
| Pin 33 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 34 | I/O — General-purpose user I/O bank 2 |
| Pin 35 | I/O — General-purpose user I/O bank 2 |
| Pin 36 | I/O — General-purpose user I/O bank 2 |
| Pin 37 | I/O — General-purpose user I/O bank 2 |
| Pin 38 | I/O — General-purpose user I/O bank 2 |
| Pin 39 | I/O — General-purpose user I/O bank 2 |
| Pin 40 | I/O — General-purpose user I/O bank 2 |
| Pin 41 | I/O — General-purpose user I/O bank 2 |
| Pin 42 | GND — Ground |
| Pin 43 | I/O — General-purpose user I/O bank 3 |
| Pin 44 | I/O — General-purpose user I/O bank 3 |
| Pin 45 | I/O — General-purpose user I/O bank 3 |
| Pin 46 | I/O — General-purpose user I/O bank 3 |
| Pin 47 | I/O — General-purpose user I/O bank 3 |
| Pin 48 | I/O — General-purpose user I/O bank 3 |
| Pin 49 | I/O — General-purpose user I/O bank 3 |
| Pin 50 | I/O — General-purpose user I/O bank 3 |
| Pin 51 | I/O — General-purpose user I/O bank 3 |
| Pin 52 | I/O — General-purpose user I/O bank 3 |
| Pin 53 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 54 | I/O — General-purpose user I/O bank 3 |
| Pin 55 | I/O — General-purpose user I/O bank 3 |
| Pin 56 | I/O — General-purpose user I/O bank 3 |
| Pin 57 | I/O — General-purpose user I/O bank 3 |
| Pin 58 | I/O — General-purpose user I/O bank 3 |
| Pin 59 | I/O — General-purpose user I/O bank 3 |
| Pin 60 | I/O — General-purpose user I/O bank 3 |
| Pin 61 | I/O — General-purpose user I/O bank 3 |
| Pin 62 | VCCINT — Core supply voltage (1.0 V typical) |
| Pin 63 | GND — Ground |
| Pin 64 | I/O — General-purpose user I/O bank 4 |
| Pin 65 | I/O — General-purpose user I/O bank 4 |
| Pin 66 | I/O — General-purpose user I/O bank 4 |
| Pin 67 | I/O — General-purpose user I/O bank 4 |
| Pin 68 | I/O — General-purpose user I/O bank 4 |
| Pin 69 | I/O — General-purpose user I/O bank 4 |
| Pin 70 | I/O — General-purpose user I/O bank 4 |
| Pin 71 | I/O — General-purpose user I/O bank 4 |
| Pin 72 | I/O — General-purpose user I/O bank 4 |
| Pin 73 | I/O — General-purpose user I/O bank 4 |
| Pin 74 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 75 | I/O — General-purpose user I/O bank 4 |
| Pin 76 | I/O — General-purpose user I/O bank 4 |
| Pin 77 | I/O — General-purpose user I/O bank 4 |
| Pin 78 | I/O — General-purpose user I/O bank 4 |
| Pin 79 | I/O — General-purpose user I/O bank 4 |
| Pin 80 | I/O — General-purpose user I/O bank 4 |
| Pin 81 | I/O — General-purpose user I/O bank 4 |
| Pin 82 | I/O — General-purpose user I/O bank 4 |
| Pin 83 | GND — Ground |
| Pin 84 | I/O — General-purpose user I/O bank 5 |
| Pin 85 | I/O — General-purpose user I/O bank 5 |
| Pin 86 | I/O — General-purpose user I/O bank 5 |
| Pin 87 | I/O — General-purpose user I/O bank 5 |
| Pin 88 | I/O — General-purpose user I/O bank 5 |
| Pin 89 | I/O — General-purpose user I/O bank 5 |
| Pin 90 | I/O — General-purpose user I/O bank 5 |
| Pin 91 | I/O — General-purpose user I/O bank 5 |
| Pin 92 | I/O — General-purpose user I/O bank 5 |
| Pin 93 | I/O — General-purpose user I/O bank 5 |
| Pin 94 | VCCIO5 — I/O bank 5 supply voltage |
| Pin 95 | I/O — General-purpose user I/O bank 5 |
| Pin 96 | I/O — General-purpose user I/O bank 5 |
| Pin 97 | I/O — General-purpose user I/O bank 5 |
| Pin 98 | I/O — General-purpose user I/O bank 5 |
| Pin 99 | I/O — General-purpose user I/O bank 5 |
| Pin 100 | I/O — General-purpose user I/O bank 5 |
| Pin 101 | I/O — General-purpose user I/O bank 5 |
| Pin 102 | I/O — General-purpose user I/O bank 5 |
| Pin 103 | VCCINT — Core supply voltage (1.0 V typical) |
| Pin 104 | GND — Ground |
| Pin 105 | I/O — General-purpose user I/O bank 6 |
| Pin 106 | I/O — General-purpose user I/O bank 6 |
| Pin 107 | I/O — General-purpose user I/O bank 6 |
| Pin 108 | I/O — General-purpose user I/O bank 6 |
| Pin 109 | I/O — General-purpose user I/O bank 6 |
| Pin 110 | I/O — General-purpose user I/O bank 6 |
| Pin 111 | I/O — General-purpose user I/O bank 6 |
| Pin 112 | I/O — General-purpose user I/O bank 6 |
| Pin 113 | I/O — General-purpose user I/O bank 6 |
| Pin 114 | I/O — General-purpose user I/O bank 6 |
| Pin 115 | VCCIO6 — I/O bank 6 supply voltage |
| Pin 116 | I/O — General-purpose user I/O bank 6 |
| Pin 117 | I/O — General-purpose user I/O bank 6 |
| Pin 118 | I/O — General-purpose user I/O bank 6 |
| Pin 119 | I/O — General-purpose user I/O bank 6 |
| Pin 120 | I/O — General-purpose user I/O bank 6 |
| Pin 121 | I/O — General-purpose user I/O bank 6 |
| Pin 122 | I/O — General-purpose user I/O bank 6 |
| Pin 123 | I/O — General-purpose user I/O bank 6 |
| Pin 124 | GND — Ground |
| Pin 125 | I/O — General-purpose user I/O bank 7 |
| Pin 126 | I/O — General-purpose user I/O bank 7 |
| Pin 127 | I/O — General-purpose user I/O bank 7 |
| Pin 128 | I/O — General-purpose user I/O bank 7 |
| Pin 129 | I/O — General-purpose user I/O bank 7 |
| Pin 130 | I/O — General-purpose user I/O bank 7 |
| Pin 131 | I/O — General-purpose user I/O bank 7 |
| Pin 132 | I/O — General-purpose user I/O bank 7 |
| Pin 133 | I/O — General-purpose user I/O bank 7 |
| Pin 134 | VCCIO7 — I/O bank 7 supply voltage |
| Pin 135 | I/O — General-purpose user I/O bank 7 |
| Pin 136 | I/O — General-purpose user I/O bank 7 |
| Pin 137 | I/O — General-purpose user I/O bank 7 |
| Pin 138 | I/O — General-purpose user I/O bank 7 |
| Pin 139 | I/O — General-purpose user I/O bank 7 |
| Pin 140 | I/O — General-purpose user I/O bank 7 |
| Pin 141 | I/O — General-purpose user I/O bank 7 |
| Pin 142 | I/O — General-purpose user I/O bank 7 |
| Pin 143 | GND — Ground |
| Pin 144 | I/O — General-purpose user I/O bank 8 |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10CL025YE144C6G is suitable for 6 applications: Industrial Machine Vision Front-End, Motor Control and Drive Front-End, Low-Power Video Bridging and Format Conversion, Factory Automation I/O Expansion and Protocol Conversion, Portable Test and Measurement Instrumentation, Legacy Cyclone IV / MAX II Footprint Migration.
Industrial Machine Vision Front-End
The 10CL025YE144C6G is well-suited to low-resolution machine-vision front-ends because its 24,624 LEs, 156 18x18 multipliers, and 608 Kbit embedded RAM are sized for typical line-buffer, Bayer demosaic, and thresholding pipelines. At 6G speed grade the multipliers run at ~225 MHz, which comfortably handles Camera-Link or MIPI-CSI2 sensor tap demosaic at 60-110 fps. The 76 user I/Os expose ample LVDS pairs for direct sensor connection. Cyclone 10 LP's lower static power vs Cyclone IV keeps vision-card thermal envelopes under 1 W for fanless embedded inspection chassis.
Recommended
Motor Control and Drive Front-End
The 10CL025YE144C6G serves as a digital front-end for BLDC, PMSM, and stepper motor control. Its 156 hardware 18x18 multipliers handle Park/Clarke transforms and PI loops without taxing the LE fabric; the 608 Kbit block RAM stores reference tables and field-orientation sin/cos lookup values; 4 PLLs derive the PWM-aligned switching clocks from a single crystal. The 144-LQFP package exposes enough LVDS-capable I/O for encoder, Hall-sensor, and resolver inputs. Compared to a software-DSP MCU implementation, the FPGA delivers deterministic PWM edge latency and concurrent commutation loops.
Recommended
Low-Power Video Bridging and Format Conversion
The 10CL025YE144C6G bridges video formats (e.g. BT.656, BT.1120, parallel RGB, MIPI-CSI2 to LVDS) and performs scaling, color-space conversion, and frame-rate adaptation. The 608 Kbit M9K RAM acts as a line buffer, and the 76 user I/Os aggregate enough LVDS lanes for 1080p60 input with sufficient margin. At 6G speed grade the fabric comfortably meets 148.5 MHz pixel clock timing for HD-SDI/HDMI 720p/1080i bridging. Cyclone 10 LP's low static power keeps the bridge under 0.8 W typical, suitable for fanless panel and KVM use.
Recommended
Factory Automation I/O Expansion and Protocol Conversion
The 10CL025YE144C6G consolidates multiple industrial protocols (EtherCAT, PROFINET, Modbus RTU/TCP, CANopen, RS-485) on a single low-power device. The 24K LEs easily absorb the soft-IP cores plus glue logic, and the 4 PLLs derive multiple independent communication clocks from one crystal. The 144-LQFP-EP package's 76 user I/Os allow 4-8 physical RS-485 transceivers, isolated CAN interfaces, and digital I/O without an additional bridge chip. The commercial temperature grade 0-85C is adequate for cabinet-mounted PLCs and remote I/O racks.
Recommended
Portable Test and Measurement Instrumentation
The 10CL025YE144C6G powers portable oscilloscopes, logic analyzers, and protocol analyzers. Its logic density is sufficient for trigger logic, decoders (I2C/SPI/UART/CAN/LIN), and on-chip waveform memory addressing; the 156 multipliers accelerate FFT/DFT pre-processing for spectrum-analyzer views. Cyclone 10 LP's lower static power vs Cyclone IV extends battery run-time in handheld scopes by 20-30%. The 144-LQFP-EP exposed pad enables a compact 4-layer PCB implementation with adequate heat removal at the 0.8 W typical operating point.
Recommended
Legacy Cyclone IV / MAX II Footprint Migration
The 10CL025YE144C6G shares its 144-LQFP-EP footprint with Cyclone IV EP4CE25 and MAX II/MAX V 240-570-LE devices, making it a clean in-place migration target when designs outgrow legacy Cyclone IV power budgets or when MAX V LE density is no longer sufficient. Quartus Prime 18.0+ ingests legacy Cyclone IV project files with limited re-work; the 6G speed grade provides tighter Fmax than the Cyclone IV C8 bin. This enables product refreshes without PCB re-spin, qualification re-test, or connector re-tooling.
Recommended
Recommended Products Summary
Engineering reference data for 10CL025YE144C6G — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10CL025YE144I7G | 10CL025YE144C8G | 10CL025YE144A7G | 10CL016YE144C6G | 10CL010YE144C6G | 10CL006YE144C6G |
|---|---|---|---|---|---|---|---|
| Package | 144-LQFP Exposed Pad (EQFP-144) | 144-LQFP Exposed Pad - same | 144-LQFP Exposed Pad - same | 144-LQFP Exposed Pad - same | 144-LQFP Exposed Pad - same | 144-LQFP Exposed Pad - same | 144-LQFP Exposed Pad - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Logic Elements | 24,624 | 24,624 | 24,624 | 24,624 | 15,408 (-37%) | 10,320 (-58%) | 6,273 (-75%) |
| Embedded Memory (bits) | 608,256 | 608,256 | 608,256 | 608,256 | 504,576 (-17%) | 414,720 (-32%) | 270,336 (-56%) |
| 18x18 Multipliers | 156 | 156 | 156 | 156 | 112 (-28%) | 72 (-54%) | 30 (-81%) |
| User I/O | 76 | 76 | 76 | 76 | 76 (same) | 76 (same) | 76 (same) |
| Speed Grade | 6G (fastest commercial) | 7G (industrial) | 8G (slower commercial) | 7G (automotive-style extended) | 6G | 6G | 6G |
| Operating Temperature | 0C to +85C (commercial) | -40C to +100C (industrial) | 0C to +85C (commercial) | Extended automotive-style | 0C to +85C | 0C to +85C | 0C to +85C |
Key Differentiators
- 6G speed grade is the fastest commercial Cyclone 10 LP bin in 144-EQFP (vs 10CL025YE144C8G)
- 60 nm Cyclone 10 LP process reduces static power vs Cyclone IV (vs EP4CE25F23 (Cyclone IV E, 144-FBGA not EQFP))
- Same-die across 25K LE OPNs enables single-board product family (vs 10CL040YE144C6G)
Design Notes
The 10CL025YE144C6G requires three independent power rails: VCCINT (1.0 V core), VCCIOx (1.2/1.5/1.8/2.5/3.3 V per bank), and VCCA (2.5 V PLL analog). Estimated: total steady-state power for a 25K LE design at 50 MHz toggle and 50% utilization is approximately 0.4-0.8 W, dominated by static Icc. Decouple each VCCINT pin with a 0.1 uF X7R ceramic plus a 10 uF bulk cap within 5 mm; VCCA needs a ferrite bead + 10 uF/0.1 uF pair. Power sequencing must enable VCCINT before VCCIO and VCCA, otherwise the POR (power-on-reset) circuit can latch the device in an undefined state.
The 144-LQFP exposed pad is the primary heat-removal path; the package datasheet specifies theta_JB of approximately 18 C/W and theta_JC-top of approximately 18 C/W. With 0.8 W typical dissipation and a copper pour of 1 square inch on a 4-layer board, junction-to-ambient theta_JA is approximately 30 C/W, giving 24 C rise at room temperature. Exposed pad must be soldered to the copper pour with a 9- or 16-thermal-via array (0.3 mm drill, 0.5 mm pitch). Inadequate thermal via design is the most common cause of 10CL025 field failures.
Cyclone 10 LP supports single-ended I/O at 1.2-3.3 V per bank and LVDS up to 840 Mbps in True-LVDS mode. Place a 100 nF decoupling cap within 2 mm of every VCCIO/VCCINT/VCCA pin, and a 10 uF bulk cap per rail. JTAG chain routing should keep TCK short and shielded by a GND guard trace. Configuration flash (EPCS or compatible) must be placed within 25 mm of the nCONFIG/nSTATUS/ASDO/DATA0 pins, with a 100 ohm series-termination resistor on DATA0. Estimated: with 76 user I/Os at 50% LVDS usage, total route-out requires a 4-layer stackup with continuous GND plane under the BGA fan-out area.
At 6G speed grade, the 18x18 multipliers sustain 225 MHz and M9K RAM sustains 315 MHz. Long combinational paths (>20 LEs) should be registered; avoid using LE outputs directly to drive global clock nets - route via dedicated clock networks (GCLK) or use PLL outputs. For SDR/DDR memories, place read/write data traces with matched length (delta <50 mil) and use source-synchronous DQS centering via the per-bank PLL. Skipping the per-bank DQS calibration is a common pitfall that causes intermittent DDR failures.
Common pitfalls: (1) Forget the exposed-pad solder connection - causes thermal runaway at >0.5 W; (2) Configure VCCIO at 1.2 V but drive 3.3 V logic, damaging I/O cells - respect VCCIO < absolute max VCCIO+0.5 V; (3) Do not leave MSEL[2..0] floating - tie to VCCINT or GND to select Active Serial vs JTAG-only configuration; (4) Forgetting to instantiate the RESET block leaves PLL outputs glitching after reconfiguration - always include ALTPLL#reset ports; (5) Without Quartus Pin Planner assignments the Fitter may swap pin functions in revisions, silently breaking PCB nets - pin-locks must be saved with the project.
Compliance Information
Lead-free 144-LQFP-EP package, RoHS and REACH compliant per Intel/Altera product page. No AEC-Q100 qualification on the standard 6G OPN; the A7G suffix denotes automotive-style extended temperature. Halogen-free per JEDEC JS709.
