5M160ZT100I5N - MAX V CPLD, 128 Macro, 100-TQFP | Intel
MPN: 5M160ZT100I5N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5.6 | $5.60 |
| 10 | $5.32 | $53.20 |
| 100 | $4.95 | $495.00 |
| 500 | $4.52 | $2,260.00 |
| 1,000 | $4.1 | $4,100.00 |
Drop-in alternatives for 5M160ZT100I5N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet β5M160ZT100I5N Maximum Ratings & Electrical Characteristics
| Family | MAX V |
| Series | 5M160Z |
| Macro Cells | 128 |
| Logic Elements (LEs) | 160 |
| Number of I/O | 79 (max user I/Os) |
| Maximum Internal Frequency | 118.3 MHz |
| Pin-to-Pin Delay (tPD) | 7.5 ns |
| Core Voltage (VCCINT) | 1.8 V |
| I/O Voltage (VCCIO) | 1.2 V to 3.3 V (multi-voltage LVCMOS/LVTTL) |
| User Flash Memory | 8 Kbits |
| Package | 100-pin TQFP (T100) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40 Β°C to +100 Β°C (industrial) |
| Programmability | In-system via JTAG (IEEE 1149.1) |
| Configuration Memory | Non-volatile (flash-backed EEPROM) |
| RoHS Status | Compliant |
5M160ZT100I5N Pin Configuration
| Pin 1 | GND β Ground |
| Pin 2 | I/O β User I/O (Bank 1) |
| Pin 3 | I/O β User I/O (Bank 1) |
| Pin 4 | I/O β User I/O (Bank 1) |
| Pin 5 | I/O β User I/O (Bank 1) |
| Pin 6 | I/O β User I/O (Bank 1) |
| Pin 7 | I/O β User I/O (Bank 1) |
| Pin 8 | I/O β User I/O (Bank 1) |
| Pin 9 | I/O β User I/O (Bank 1) |
| Pin 10 | I/O β User I/O (Bank 1) |
| Pin 11 | VCCIO1 β Bank 1 I/O supply voltage |
| Pin 12 | I/O β User I/O (Bank 1) |
| Pin 13 | I/O β User I/O (Bank 1) |
| Pin 14 | I/O β User I/O (Bank 1) |
| Pin 15 | I/O β User I/O (Bank 1) |
| Pin 16 | GND β Ground |
| Pin 17 | I/O β User I/O (Bank 2) |
| Pin 18 | I/O β User I/O (Bank 2) |
| Pin 19 | I/O β User I/O (Bank 2) |
| Pin 20 | I/O β User I/O (Bank 2) |
| Pin 21 | I/O β User I/O (Bank 2) |
| Pin 22 | I/O β User I/O (Bank 2) |
| Pin 23 | I/O β User I/O (Bank 2) |
| Pin 24 | VCCIO2 β Bank 2 I/O supply voltage |
| Pin 25 | I/O β User I/O (Bank 2) |
| Pin 26 | I/O β User I/O (Bank 2) |
| Pin 27 | I/O β User I/O (Bank 2) |
| Pin 28 | I/O β User I/O (Bank 2) |
| Pin 29 | I/O β User I/O (Bank 2) |
| Pin 30 | GND β Ground |
| Pin 31 | I/O β User I/O (Bank 2) |
| Pin 32 | I/O β User I/O (Bank 2) |
| Pin 33 | VCCINT β Core supply voltage (1.8 V) |
| Pin 34 | I/O β User I/O (Bank 2) |
| Pin 35 | I/O β User I/O (Bank 2) |
| Pin 36 | I/O β User I/O (Bank 2) |
| Pin 37 | I/O β User I/O (Bank 2) |
| Pin 38 | I/O β User I/O (Bank 2) |
| Pin 39 | I/O β User I/O (Bank 2) |
| Pin 40 | I/O β User I/O (Bank 2) |
| Pin 41 | I/O β User I/O (Bank 2) |
| Pin 42 | GND β Ground |
| Pin 43 | I/O β User I/O (Bank 3) |
| Pin 44 | I/O β User I/O (Bank 3) |
| Pin 45 | I/O β User I/O (Bank 3) |
| Pin 46 | I/O β User I/O (Bank 3) |
| Pin 47 | I/O β User I/O (Bank 3) |
| Pin 48 | VCCIO3 β Bank 3 I/O supply voltage |
| Pin 49 | I/O β User I/O (Bank 3) |
| Pin 50 | I/O β User I/O (Bank 3) |
| Pin 51 | I/O β User I/O (Bank 3) |
| Pin 52 | I/O β User I/O (Bank 3) |
| Pin 53 | I/O β User I/O (Bank 3) |
| Pin 54 | GND β Ground |
| Pin 55 | I/O β User I/O (Bank 3) |
| Pin 56 | I/O β User I/O (Bank 3) |
| Pin 57 | I/O β User I/O (Bank 3) |
| Pin 58 | I/O β User I/O (Bank 3) |
| Pin 59 | I/O β User I/O (Bank 3) |
| Pin 60 | VCCINT β Core supply voltage (1.8 V) |
| Pin 61 | I/O β User I/O (Bank 3) |
| Pin 62 | I/O β User I/O (Bank 3) |
| Pin 63 | I/O β User I/O (Bank 3) |
| Pin 64 | I/O β User I/O (Bank 4) |
| Pin 65 | I/O β User I/O (Bank 4) |
| Pin 66 | GND β Ground |
| Pin 67 | I/O β User I/O (Bank 4) |
| Pin 68 | VCCIO4 β Bank 4 I/O supply voltage |
| Pin 69 | I/O β User I/O (Bank 4) |
| Pin 70 | I/O β User I/O (Bank 4) |
| Pin 71 | I/O β User I/O (Bank 4) |
| Pin 72 | I/O β User I/O (Bank 4) |
| Pin 73 | I/O β User I/O (Bank 4) |
| Pin 74 | I/O β User I/O (Bank 4) |
| Pin 75 | GND β Ground |
| Pin 76 | I/O β User I/O (Bank 4) |
| Pin 77 | I/O β User I/O (Bank 4) |
| Pin 78 | I/O β User I/O (Bank 4) |
| Pin 79 | I/O β User I/O (Bank 4) |
| Pin 80 | I/O β User I/O (Bank 4) |
| Pin 81 | I/O β User I/O (Bank 4) |
| Pin 82 | VCCINT β Core supply voltage (1.8 V) |
| Pin 83 | TDI β JTAG Test Data In (Bank 1) |
| Pin 84 | TMS β JTAG Test Mode Select (Bank 1) |
| Pin 85 | TCK β JTAG Test Clock (Bank 1) |
| Pin 86 | VCCIO1 β Bank 1 I/O supply voltage |
| Pin 87 | I/O β User I/O (Bank 1) |
| Pin 88 | I/O β User I/O (Bank 1) |
| Pin 89 | I/O β User I/O (Bank 1) |
| Pin 90 | I/O β User I/O (Bank 1) |
| Pin 91 | GND β Ground |
| Pin 92 | I/O β User I/O (Bank 1) |
| Pin 93 | I/O β User I/O (Bank 1) |
| Pin 94 | I/O β User I/O (Bank 1) |
| Pin 95 | I/O β User I/O (Bank 1) |
| Pin 96 | I/O β User I/O (Bank 1) |
| Pin 97 | I/O β User I/O (Bank 1) |
| Pin 98 | I/O β User I/O (Bank 1) |
| Pin 99 | I/O β User I/O (Bank 1) |
| Pin 100 | TDO β JTAG Test Data Out (Bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M160ZT100I5N is suitable for 6 applications: Industrial I/O Expansion and Glue Logic, FPGA / ASIC Companion Configuration and Boot Sequencer, Bus Interface Bridges (IΒ²C, SPI, UART, Parallel), LED Display Drivers and Signage Controllers, Power Sequencing and Hot-Swap Controllers, Automotive Infotainment and Body Electronics.
Industrial I/O Expansion and Glue Logic
The 5M160ZT100I5N is well suited to industrial I/O expansion as a glue-logic bridge between microcontrollers, sensors, and actuators. With 79 user I/Os and multi-voltage support from 1.2 V to 3.3 V, it can translate between legacy 3.3 V microcontroller buses and modern 1.8 V peripherals without external level shifters. The 7.5 ns tPD enables deterministic decoding of address and chip-select lines in real-time PLC backplanes, while the industrial -40 Β°C to +100 Β°C range covers factory-floor and outdoor cabinet environments. Its non-volatile instant-on configuration eliminates boot PROM complexity in safety-critical industrial controllers.
Recommended
FPGA / ASIC Companion Configuration and Boot Sequencer
As a companion to FPGAs such as Cyclone V or Cyclone 10 LP, the 5M160ZT100I5N serves as a deterministic boot sequencer that holds FPGAs in reset, sequences power rails, and releases configuration pins in the correct order. Its non-volatile flash-backed configuration powers up in microseconds without external boot memory, making it ideal when FPGA configuration time is critical. The 1.8 V VCCINT matches the FPGAs in the Cyclone V family, while multi-voltage I/O banks allow direct connection to 2.5 V or 3.3 V support circuitry without external level shifting.
Recommended
Bus Interface Bridges (IΒ²C, SPI, UART, Parallel)
The 5M160ZT100I5N excels as a protocol-bridging device when a system needs to connect an IΒ²C master to an SPI slave, or convert a parallel 8-bit bus to a serial UART. Its 128 macro cells comfortably fit state-machine implementations of common protocols, while the 7.5 ns tPD meets the setup-and-hold requirements of 400 kHz Fast-Mode IΒ²C and 10 MHz SPI. Multi-voltage I/O (1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V) lets the CPLD sit between two devices of incompatible logic levels without a discrete translator, saving board area and BOM cost.
Recommended
LED Display Drivers and Signage Controllers
LED matrix displays and signage controllers use the 5M160ZT100I5N for row/column scanning, PWM dimming, and timing generation. Its 79 user I/Os can drive multiple 8-bit shift-register chains in parallel, refreshing 64Γ32 RGB LED panels at typical 1:16 scan rates without external logic. The 1.8 V core keeps power consumption low in always-on digital-signage applications, while the multi-voltage I/O directly interfaces to 3.3 V or 5 V LED-driver ICs. Industrial temperature rating supports outdoor and semi-outdoor installations such as transit-information displays and retail signage.
Recommended
Power Sequencing and Hot-Swap Controllers
The 5M160ZT100I5N provides deterministic multi-rail power-up and power-down sequencing in ATCA, MicroTCA, and ATX systems where the order of rail rise/fall times is critical to ASIC and FPGA reliability. With 128 macro cells and 79 user I/Os, the CPLD can sequence 6-8 independent rails with programmable delays, monitor power-good signals, and assert/clear reset lines. The non-volatile instant-on behavior means the sequencing logic is active as soon as the 1.8 V rail comes up, without waiting for an FPGA to be configured. JTAG access enables in-system reprogramming of sequencing parameters during board bring-up.
Recommended
Automotive Infotainment and Body Electronics
The 5M160ZT100I5N is used in automotive infotainment head units, instrument clusters, and body-electronics modules as glue logic, CAN/LIN gateway controllers, and backlight drivers. The industrial -40 Β°C to +100 Β°C temperature range covers cabin environments, and the AEC-Q100-grade sibling 5M160ZT100A5N extends coverage to under-hood applications. With multi-voltage I/O support, the CPLD bridges 3.3 V microcontrollers to 5 V body-control bus peripherals, while the JTAG interface enables end-of-line boundary-scan testing for automotive quality assurance.
Recommended
Recommended Products Summary
Engineering reference data for 5M160ZT100I5N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M160ZT100C5N | 5M160ZT100A5N | 5M160ZT100I5 | 5M160ZT100C4N |
|---|---|---|---|---|---|
| Package | 100-pin TQFP | 100-pin TQFP - same | 100-pin TQFP - same | 100-pin TQFP - same | 100-pin TQFP - same |
| Brand | Intel | Intel | Intel | Intel | Intel |
| Macro Cells | 128 | 128 | 128 | 128 | 128 |
| Logic Elements | 160 | 160 | 160 | 160 | 160 |
| Maximum User I/Os | 79 | 79 | 79 | 79 | 79 |
| Pin-to-Pin Delay (tPD) | 7.5 ns | 7.5 ns | 7.5 ns | 7.5 ns | 10 ns (slower -8 speed grade) |
| Maximum Internal Frequency | 118.3 MHz | 118.3 MHz | 118.3 MHz | 118.3 MHz | [DATA_NEEDED] |
| Operating Temperature | -40 Β°C to +100 Β°C (industrial) | 0 Β°C to +85 Β°C (commercial) | -40 Β°C to +125 Β°C (automotive AEC-Q100) | -40 Β°C to +100 Β°C (industrial) | 0 Β°C to +85 Β°C (commercial) |
| Core Voltage (VCCINT) | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Speed Grade | -5 | -5 | -5 | -5 | -4 (slower) |
| Unit Price (1-piece, USD) | 5.60 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Highest I/O count in the 5M160Z family (vs 5M160ZM100I5N)
- Industrial -40 Β°C to +100 Β°C operating range (vs 5M160ZT100C5N)
- Non-volatile instant-on configuration (vs Xilinx XC2C128-7VQG100C)
Design Notes
The 5M160ZT100I5N operates from a 1.8 V VCCINT core supply with four independent VCCIO banks (VCCIO1-VCCIO4) supporting 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V LVCMOS and LVTTL. Place one 0.1 Β΅F decoupling capacitor within 5 mm of every VCCINT pin and one 0.1 Β΅F + 10 Β΅F bulk capacitor near each VCCIO bank pin. JTAG pins (TMS, TDI, TDO, TCK) reside in Bank 1, so VCCIO1 must be present for boundary-scan to function even when Bank 1 is unused for application I/O.
Route JTAG signals (TMS, TDI, TDO, TCK) as a daisy-chain across all JTAG-compliant devices on the board, with 10 kΞ© pull-ups on TMS, TDI, and TCK to their respective VCCIO bank supply. Keep TCK rise/fall times under 10 ns; if driving multiple devices, buffer TCK locally at each TAP. For multi-voltage systems, ensure that each VCCIO bank is driven by its own regulator so that the CPLD can be partially powered-down without back-powering unused I/O pins.
Do not apply signal voltage to any I/O pin before its corresponding VCCIO bank is powered - the absolute-maximum rating is VCCIO + 0.3 V with diode-clamping. Do not use 5 V inputs even on 3.3 V-tolerant banks; MAX V banks are NOT 5 V-tolerant. When migrating from the 5M160Z A-speed grade (-A5N) to the C or I grade, the JTAG IDCODE is identical but DC and AC specifications differ - re-validate timing closure in Quartus Prime.
Estimated: At maximum toggle activity across all 79 I/Os at 100 MHz with 3.3 V VCCIO, the 5M160ZT100I5N can dissipate up to approximately 200 mW, raising the junction temperature roughly 13 Β°C above ambient on a standard 4-layer JEDEC EIA/JESD51 test board (ΞΈJA β 65 Β°C/W for TQFP-100). For sustained high-toggle industrial environments, route copper pours on the top and inner layers under the exposed thermal slug area to keep Tj below 100 Β°C.
Compliance Information
RoHS and REACH compliant per Intel product page. Standard 5M160ZT100I5N is NOT AEC-Q100 qualified; choose the 5M160ZT100A5N variant for automotive AEC-Q100 applications.
