5M160ZE64I5N - 160 Logic Element MAX V CPLD | Intel | 64-EQFP
MPN: 5M160ZE64I5N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6.36 | $6.36 |
| 10 | $5.73 | $57.30 |
| 100 | $5.16 | $516.00 |
| 500 | $4.65 | $2,325.00 |
| 1,000 | $4.13 | $4,130.00 |
Drop-in alternatives for 5M160ZE64I5N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet β5M160ZE64I5N Maximum Ratings & Electrical Characteristics
| Device Family | MAX V |
| Logic Elements (LEs) | 160 |
| Macrocells | 128 |
| Maximum User I/O Pins | 79 |
| Pin-to-Pin Logic Delay (tPD) | 7.5 ns |
| User Flash Memory | 4.0 Kbits |
| Logic Array Blocks (LABs) | 4 |
| Supply Voltage - Core | 3.3 V or 2.5 V |
| I/O Bank Voltages | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Operating Temperature | -40C to +100C (Industrial) |
| Package | 64-pin EQFP (Exposed Pad) |
| Mounting Type | Surface Mount |
| JTAG Support | Yes (IEEE 1149.1, TMS/TDI/TDO/TCK) |
| Differential I/O | LVDS, RSDS, mini-LVDS, LVPECL (emulated) |
| Configuration | Non-volatile on-chip flash, instant-on |
| RoHS Status | Compliant |
5M160ZE64I5N Pin Configuration
| Pin 1 | I/O β General-purpose user I/O (Bank 1) |
| Pin 2 | I/O β General-purpose user I/O (Bank 1) |
| Pin 3 | I/O β General-purpose user I/O (Bank 1) |
| Pin 4 | I/O β General-purpose user I/O (Bank 1) |
| Pin 5 | I/O β General-purpose user I/O (Bank 1) |
| Pin 6 | I/O β General-purpose user I/O (Bank 1) |
| Pin 7 | I/O β General-purpose user I/O (Bank 1) |
| Pin 8 | I/O β General-purpose user I/O (Bank 1) |
| Pin 9 | GND β Ground |
| Pin 10 | I/O β General-purpose user I/O (Bank 1) |
| Pin 11 | I/O β General-purpose user I/O (Bank 1) |
| Pin 12 | I/O β General-purpose user I/O (Bank 1) |
| Pin 13 | I/O β General-purpose user I/O (Bank 1) |
| Pin 14 | I/O β General-purpose user I/O (Bank 1) |
| Pin 15 | TDI β JTAG Test Data In (Bank 1) |
| Pin 16 | TMS β JTAG Test Mode Select (Bank 1) |
| Pin 17 | TCK β JTAG Test Clock (Bank 1) |
| Pin 18 | I/O β General-purpose user I/O (Bank 1) |
| Pin 19 | I/O β General-purpose user I/O (Bank 1) |
| Pin 20 | I/O β General-purpose user I/O (Bank 1) |
| Pin 21 | I/O β General-purpose user I/O (Bank 1) |
| Pin 22 | I/O β General-purpose user I/O (Bank 1) |
| Pin 23 | VCCIO1 β I/O Bank 1 supply voltage |
| Pin 24 | I/O β General-purpose user I/O (Bank 1) |
| Pin 25 | I/O β General-purpose user I/O (Bank 1) |
| Pin 26 | I/O β General-purpose user I/O (Bank 1) |
| Pin 27 | I/O β General-purpose user I/O (Bank 2) |
| Pin 28 | I/O β General-purpose user I/O (Bank 2) |
| Pin 29 | I/O β General-purpose user I/O (Bank 2) |
| Pin 30 | I/O β General-purpose user I/O (Bank 2) |
| Pin 31 | I/O β General-purpose user I/O (Bank 2) |
| Pin 32 | GND β Ground |
| Pin 33 | I/O β General-purpose user I/O (Bank 2) |
| Pin 34 | I/O β General-purpose user I/O (Bank 2) |
| Pin 35 | I/O β General-purpose user I/O (Bank 2) |
| Pin 36 | I/O β General-purpose user I/O (Bank 2) |
| Pin 37 | I/O β General-purpose user I/O (Bank 2) |
| Pin 38 | I/O β General-purpose user I/O (Bank 2) |
| Pin 39 | I/O β General-purpose user I/O (Bank 2) |
| Pin 40 | I/O β General-purpose user I/O (Bank 2) |
| Pin 41 | I/O β General-purpose user I/O (Bank 2) |
| Pin 42 | VCCIO2 β I/O Bank 2 supply voltage |
| Pin 43 | I/O β General-purpose user I/O (Bank 2) |
| Pin 44 | I/O β General-purpose user I/O (Bank 2) |
| Pin 45 | I/O β General-purpose user I/O (Bank 2) |
| Pin 46 | I/O β General-purpose user I/O (Bank 2) |
| Pin 47 | I/O β General-purpose user I/O (Bank 2) |
| Pin 48 | I/O β General-purpose user I/O (Bank 2) |
| Pin 49 | GND β Ground |
| Pin 50 | TDO β JTAG Test Data Out (Bank 1) |
| Pin 51 | I/O β General-purpose user I/O (Bank 2) |
| Pin 52 | I/O β General-purpose user I/O (Bank 2) |
| Pin 53 | I/O β General-purpose user I/O (Bank 2) |
| Pin 54 | I/O β General-purpose user I/O (Bank 2) |
| Pin 55 | I/O β General-purpose user I/O (Bank 2) |
| Pin 56 | VCCINT β Core supply voltage (3.3 V or 2.5 V) |
| Pin 57 | I/O β General-purpose user I/O (Bank 2) |
| Pin 58 | I/O β General-purpose user I/O (Bank 2) |
| Pin 59 | I/O β General-purpose user I/O (Bank 2) |
| Pin 60 | I/O β General-purpose user I/O (Bank 2) |
| Pin 61 | I/O β General-purpose user I/O (Bank 2) |
| Pin 62 | I/O β General-purpose user I/O (Bank 2) |
| Pin 63 | I/O β General-purpose user I/O (Bank 2) |
| Pin 64 | I/O β General-purpose user I/O (Bank 2) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
5M160ZE64I5N is suitable for 6 applications: Industrial I/O Expansion and Level Translation, Glue Logic for Microprocessors and DSPs, Power-Up Sequencing for Multi-Rail Systems, JTAG Chain Management and Boundary Scan, LED Display and Signage Driving, State Machine Replacement in Embedded Controls.
Industrial I/O Expansion and Level Translation
The 5M160ZE64I5N is widely used to expand I/O count and bridge voltage domains on industrial control boards where the host processor lacks enough GPIOs or operates at a different logic level than the peripherals. Its 79 maximum user I/O pins and MultiVolt I/O banks (1.5 V to 3.3 V per bank) let a single device translate between a 1.8 V SoC and 3.3 V or 5 V-tolerant peripherals in one chip. Compared with discrete 74-series translators, the CPLD approach is one IC instead of ten, saving PCB area and BOM cost while remaining instantly reconfigurable for late design changes.
Recommended
Glue Logic for Microprocessors and DSPs
Designers use the 5M160ZE64I5N as modern 'glue logic' to combine address decoding, chip-select generation, wait-state insertion, and interrupt steering between a microprocessor and its memory/peripheral bus. With a 7.5 ns pin-to-pin delay, the device comfortably meets the timing budgets of 50 MHz to 70 MHz external memory buses, replacing dozens of 74HC/74F-series gates in a single non-volatile package. Industrial temperature qualification and instant-on from on-chip flash make it a robust choice for embedded compute platforms that must boot deterministically in the field.
Recommended
Power-Up Sequencing for Multi-Rail Systems
The 5M160ZE64I5N excels at sequencing complex multi-rail power systems in networking, telecom, and server boards where rails must come up in a defined order to prevent latch-up or in-rush damage. Its 128 macrocells are more than enough to implement a 6 to 10-rail sequencer with adjustable delays, fault detection, and PG (power-good) handshaking. Non-volatile flash means the sequencing program is available the moment VCC is valid, before any processor on the board has booted - critical for ASICs and FPGAs that need controlled voltage ramps.
Recommended
JTAG Chain Management and Boundary Scan
The 5M160ZE64I5N is frequently placed in JTAG scan chains to bridge or extend IEEE 1149.1 boundary-scan access to downstream devices on densely populated boards. With its own JTAG TAP, the CPLD can multiplex between a board-level test access port and in-system programming of other devices, or chain multiple JTAG devices into a single daisy chain with correct TDO-to-TDI routing. This simplifies factory test fixtures and field firmware updates by centralizing all JTAG traffic through one well-characterized component.
Recommended
LED Display and Signage Driving
Commercial LED displays, traffic signs, and large-format signage boards use the 5M160ZE64I5N to multiplex rows and columns of LEDs, generate PWM dimming, and scan keypads in parallel. The device's 79 user I/O pins drive up to 64 multiplexed LEDs directly with no additional drivers for small signs, while its 7.5 ns tPD supports the sub-microsecond row scanning required for flicker-free PWM dimming at 1 kHz refresh rates. Industrial temperature rating makes it suitable for outdoor enclosures subject to summer heat and winter cold.
Recommended
State Machine Replacement in Embedded Controls
Engineers replace complex discrete state-machine implementations - especially in motor control, valve sequencing, and instrument front panels - with the 5M160ZE64I5N to consolidate 20 to 30 MSI logic chips into one programmable device. The MAX V's deterministic 7.5 ns timing guarantees worst-case state transitions, which is essential in safety-related controls where asynchronous glitches cannot be tolerated. Once a design is stable, the JTAG-programmed flash configuration becomes a locked BOM item with no firmware-update burden on the host MCU.
Recommended
Recommended Products Summary
Engineering reference data for 5M160ZE64I5N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 5M160ZE64C5N | 5M160ZE64I4N | 5M160ZE64A5N | 5M160ZE64I5 |
|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Package | 64-pin EQFP | 64-pin EQFP | 64-pin EQFP | 64-pin EQFP | 64-pin EQFP |
| Logic Elements | 160 | 160 | 160 | 160 | 160 |
| Macrocells | 128 | 128 | 128 | 128 | 128 |
| tPD (Pin-to-Pin Delay) | 7.5 ns | 7.5 ns | 9.0 ns | 7.5 ns | 7.5 ns |
| Temperature Grade | Industrial -40C to +100C | Commercial 0C to +85C | Industrial -40C to +100C | Automotive AEC-Q100 | Industrial -40C to +100C |
| Pb-Free (N suffix) | Yes (N) | Yes (N) | Yes (N) | Yes (N) | No (Pb-containing) |
| Quartus Toolchain Support | Yes (MAX V device family) | Yes | Yes | Yes | Yes |
| Approx Unit Price (qty 100) | $5.16 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Industrial temperature grade vs commercial-only drop-ins (vs 5M160ZE64C5N)
- Faster speed grade vs I4 variant (vs 5M160ZE64I4N)
- Lower-cost vs automotive AEC-Q100 grade (vs 5M160ZE64A5N)
Design Notes
The 5M160ZE64I5N core operates from VCCINT at either 3.3 V or 2.5 V, while VCCIO pins power each I/O bank independently at 1.5 V, 1.8 V, 2.5 V, or 3.3 V. Decouple every VCC pin with a 0.1 microfarad X7R ceramic capacitor placed within 3 mm of the pin, and add a 10 microfarad bulk tantalum or ceramic capacitor at each supply rail entry point. The exposed thermal pad on the EQFP package must be soldered to a continuous ground plane with at least nine thermal vias to a copper area of 1 square inch or larger for proper thermal relief.
Route the JTAG signals TMS, TDI, TDO, and TCK as a 4-wire daisy chain with TCK and TMS treated as clock-like signals - keep them short, length-matched within 25 mm, and series-terminated with 33 ohm resistors at the driver end when the chain exceeds 100 mm. Place 10 kohm pull-up resistors on TCK, TMS, TDI, and a pull-down on TDO to keep the JTAG state machine in a benign known state during board power-up, before the CPLD is configured.
Estimated: The exposed thermal pad (EP) on the EQFP-64 package is not optional. Skipping its solder connection can raise junction temperature by 15C to 25C under typical switching loads and cause intermittent logic errors at high ambient. A common mistake is also treating Bank 1 and Bank 2 as identical in JTAG mode - JTAG pins TMS, TDI, TDO, and TCK always reside in Bank 1, so VCCIO1 must remain powered whenever JTAG is in use, even if the user I/O banks are shut down for power savings.
Compliance Information
RoHS and REACH compliance per Intel/Altera product page; Pb-free confirmed by 'N' suffix. For AEC-Q100 automotive qualification, choose the 5M160ZE64A5N variant. Halogen-free status not explicitly stated in the Verified Web Data.
