A42MX09-PQG160M - 14K Gate FPGA 160-BQFP | Microchip
MPN: A42MX09-PQG160M β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $42.5 | $42.50 |
| 10 | $39.1 | $391.00 |
| 100 | $35.6 | $3,560.00 |
| 500 | $32.4 | $16,200.00 |
| 1,000 | $29.8 | $29,800.00 |
Drop-in alternatives for A42MX09-PQG160M β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
A42MX09-2PQG160M
β Drop-Inπ Reference alternative (not in catalog)
A42MX09-2PQ160M
β Drop-Inπ Reference alternative (not in catalog)
A42MX09-PQG160
β Drop-Inπ Reference alternative (not in catalog)
A42MX09-PQG160I
β Drop-Inπ Reference alternative (not in catalog)
A42MX09-PQG160M Maximum Ratings & Electrical Characteristics
| System Gates | 14000 |
| Configurable Logic Blocks (CLBs) | 336 |
| Logic Cells | 684 |
| User I/O (this package) | 101 |
| Family Max User I/O | 202 |
| Dual-Port SRAM | 2.5 kbits |
| Internal Clock Frequency | 117 MHz to 146.3 MHz (speed grade dependent) |
| Supply Voltage | 3.3 V / 5 V |
| Process Technology | 0.45 um CMOS |
| Logic Family | CMOS |
| Package | 160-BQFP (PQFP), 0.65 mm terminal pitch |
| Terminal Count | 160 |
| Mounting Type | Surface Mount |
| Package Code (JESD-30) | S-PQFP-G160 |
| Operating Temperature | Industrial (-40C to +85C), M suffix |
| Programming Type | SRAM-based, antifuse-independent |
| Boundary Scan | JTAG (TDI/TDO chain) |
| RoHS Status | Lead Free / Compliant |
A42MX09-PQG160M Pin Configuration
| Pin 1 | I/O β User-programmable input/output (assignment per DS2316 pin table) |
| Pin 12 | VCC β Core/IO supply (3.3V or 5V) - [DATA_NEEDED: exact pin assignment] |
| Pin 16 | GND β Ground - [DATA_NEEDED: exact pin assignment] |
| Pin [DATA_NEEDED: pin number] | TDI β JTAG boundary-scan test data in (start of scan chain) |
| Pin [DATA_NEEDED: pin number] | TDO β JTAG boundary-scan test data out (end of scan chain) |
| Pin [DATA_NEEDED: pin number] | TMS β JTAG test mode select |
| Pin [DATA_NEEDED: pin number] | TCK β JTAG test clock |
| Pin [DATA_NEEDED: pin number] | CLOCK β Dedicated global clock input |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
A42MX09-PQG160M is suitable for 6 applications: Industrial Control and Automation, Legacy PLD and ASIC Consolidation, 5V-Tolerant Bus Bridging, Motor Drive Interface Logic, Test and Measurement Fixtures, Aerospace and Defense Upgrade Programs.
Industrial Control and Automation
The A42MX09-PQG160M fits industrial controllers thanks to its 5V-tolerant I/O, industrial (-40C to +85C) M-grade temperature range, and 101 user I/O for driving sensors, relays, and fieldbus transceivers. Its 2.5 kbits of dual-port SRAM implement FIFOs between a processor and I/O islands, while wide-decode circuitry handles fast address decoding at full 117 MHz speed. Placed as glue logic between a PLC CPU board and backplane, it consolidates dozens of legacy 5V TTL devices into one 160-PQFP, cutting BOM count and board area with no level-shifting overhead.
Recommended
Legacy PLD and ASIC Consolidation
Microchip explicitly positions MX as a single-chip ASIC alternative for integrating legacy PLDs, PALs, and GALs into one low-cost device. The A42MX09's 684 logic cells and 14K gates absorb multiple 22V10-class PLDs plus surrounding SSI/MSI logic. Its proven 0.45um process and long-term Microchip availability commitment make it ideal for sustaining production of older industrial and mil-aero boards where redesign risk must be minimized. Migrating to the MX fabric typically requires only netlist translation in Libero SoC, preserving verified timing behavior of the original PLD equations.
Recommended
5V-Tolerant Bus Bridging
Bridging 5V legacy buses (ISA-style backplanes, VME glue logic, old peripheral interfaces) to modern 3.3V processors demands I/O that survives 5V signaling without external translators. The MX architecture natively supports 5.0V operation, so the A42MX09-PQG160M sits directly on a 5V bus while internal logic runs at compatible levels. With 101 I/O and JTAG boundary-scan on TDI/TDO chains, board-level interconnect test is supported per the DS2316 datasheet. This eliminates translator ICs, reduces propagation delay, and preserves signal integrity on long, heavily loaded legacy backplane nets.
Recommended
Motor Drive Interface Logic
In motor drives, the FPGA generates PWM gating patterns, dead-time insertion, and fault interlocks between a DSP or MCU and gate drivers. The A42MX09's wide-dedecode circuitry and deterministic fabric timing (no software jitter) make it suitable for hard-wired protection: shoot-through interlocks latch in nanoseconds independent of the processor. The 117 MHz internal frequency supports sub-10ns PWM resolution. Industrial temperature rating matches drive-ambient environments, and 5V I/O interfaces directly with older gate-driver input stages common in retrofit drive designs.
Recommended
Test and Measurement Fixtures
Bench and production test fixtures use small FPGAs for pattern generation, capture, and clock domain bridging. The A42MX09-PQG160M offers 684 logic cells, dual-port SRAM for capture buffers, and abundant I/O for driving device-under-test headers. JTAG boundary scan supports interconnect verification of the fixture itself. Because the MX family is SRAM-programmed, fixtures can be reconfigured per product variant from a host PC. Its mature process also means stable, repeatable I/O timing characteristics year over year, valuable for calibrated measurement repeatability in production environments.
Recommended
Aerospace and Defense Upgrade Programs
Microsemi (now Microchip) MX FPGAs have a long heritage in defense programs, and the A42MX09-PQG160M serves fleet upgrades of avionics and ground systems where design stability outweighs process-node novelty. The single-chip ASIC-alternative approach replaces multi-chip obsolescent logic with one procurable part, and Microchip's commitment to the MX platform protects against future obsolescence. The M-grade industrial temperature covers most sheltered defense environments. Design migration preserves verified logic via netlist translation, minimizing requalification cost, while JTAG chain support enables in-system functional test of upgraded boards.
Recommended
Recommended Products Summary
Engineering reference data for A42MX09-PQG160M β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | A42MX09-2PQG160M | A42MX09-2PQ160M | A42MX09-PQG160 |
|---|---|---|---|---|
| Package | 160-BQFP (PQFP), 0.65 mm pitch | 160-PQFP - same | 160-PQFP - same | 160-PQFP - same |
| Brand | Microchip Technology (Microsemi) | Microchip Technology | Microchip Technology | Microchip Technology |
| System Gates | 14000 | 14000 | 14000 | 14000 |
| CLBs / Logic Cells | 336 / 684 | 336 / 684 | 336 / 684 | 336 / 684 |
| User I/O | 101 | 101 | 101 | 101 |
| Max Internal Frequency | ~117 MHz (standard grade) | 146.3 MHz (speed grade 2) | 146.3 MHz (speed grade 2) | [DATA_NEEDED] |
| Temperature Range | Industrial (M suffix) | Industrial (M suffix) | Industrial (M suffix) | Commercial |
| Dual-Port SRAM | 2.5 kbits | 2.5 kbits | 2.5 kbits | 2.5 kbits |
| Process / Supply | 0.45 um CMOS, 3.3V/5V | 0.45 um CMOS, 3.3V/5V | 0.45 um CMOS, 3.3V/5V | 0.45 um CMOS, 3.3V/5V |
Key Differentiators
- Native 5.0V architecture eliminates level translation (vs Modern 3.3V FPGAs (e.g., Xilinx Spartan-class))
- Integrated 2.5 kbit dual-port SRAM (vs A42MX09-2PQG160M (same die))
- Long-term mature-node availability (vs Cross-brand competitor FPGAs)
Design Notes
The 160-PQFP has 0.65 mm terminal pitch (JESD-30 S-PQFP-G160). Use the Microchip-recommended land pattern, and route fine-pitch fanout with via-in-pad or dogbone escapes. Allocate 0.1 uF ceramic decoupling per supply pin pair placed within 5 mm of the package. The M-grade part reflows at standard lead-free profiles; follow IPC-compliant reflow per your assembler qualification.
MX I/O are software-configurable, so pin planning in Libero SoC should group bus interfaces on adjacent pins to minimize simultaneous-switching noise. Limit slew-driven ground bounce on the 101 available I/O by distributing returns across all GND pins. Because the family runs at 5V, check ringing against absolute maximum ratings when driving long backplane traces.
Do not confuse speed grades: A42MX09-PQG160M (standard) and A42MX09-2PQG160M (grade 2, 146.3 MHz) differ in timing even though they are pin-identical; timing signoff must use the grade actually purchased. Legacy Actel Designer projects must be migrated to Microchip Libero SoC for current toolchain support. Confirm dual-port SRAM allocation does not consume logic modules needed for your design.
Compliance Information
Distributor listings mark A42MX09-PQG160M as lead free (PCB Electronics: 'A42MX09-PQG160M LEAD FREE'). REACH/halogen status not stated in provided data.
