UCC21520Q-Q1 - 4A/6A 5.7kVRMS Isolated Dual Gate Driver | TI
MPN: UCC21520Q-Q1 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $4.95 | $4.95 |
| 10 | $4.46 | $44.60 |
| 100 | $3.71 | $371.00 |
| 500 | $3.22 | $1,610.00 |
| 1,000 | $2.85 | $2,850.00 |
Drop-in alternatives for UCC21520Q-Q1 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
UCC21520
β Drop-Inβ In Stock
$1.79 / Unit
View Datasheet βUCC21521
β Drop-Inβ In Stock
$1.82 / Unit
View Datasheet βUCC21530
β Drop-Inβ In Stock
$2.41 / Unit
View Datasheet βUCC21550
β‘ Same Packageβ In Stock
$1.25 / Unit
View Datasheet βNCP51705
β‘ Same Packageπ Reference alternative (not in catalog)
UCC21520Q-Q1 Maximum Ratings & Electrical Characteristics
| Output Configuration | Dual-channel isolated gate driver |
| Peak Source Current | 4 A |
| Peak Sink Current | 6 A |
| Isolation Rating | 5.7 kVRMS (reinforced) |
| Isolation Technology | Capacitive (SiO2) |
| CMTI | 125 V/ns minimum |
| Maximum Switching Frequency | 5 MHz |
| UVLO | Yes, on all supply pins (8-V UVLO variant) |
| Input Threshold | TTL and CMOS compatible, independent of VDD |
| Control Pins | INA, INB, DIS (disable) |
| Target Power Devices | Power MOSFETs, IGBTs, SiC MOSFETs |
| Package | 16-SOIC wide-body (DWQ), surface mount |
| Automotive Qualification | AEC-Q100 (Q1) |
| Propagation Delay | [DATA_NEEDED: typical propagation delay value] |
| Operating Temperature | [DATA_NEEDED: operating temperature range] |
| RoHS Status | Compliant |
UCC21520Q-Q1 Pin Configuration
| Pin 1 | VCCI β Input-side supply voltage |
| Pin 2 | GND β Input-side ground reference |
| Pin 3 | INB β Input B (TTL/CMOS compatible) |
| Pin 4 | INA β Input A (TTL/CMOS compatible) |
| Pin 5 | DIS β Disable input (high disables outputs) |
| Pin 6 | NC β No connect (isolation clearance) |
| Pin 7 | NC β No connect (isolation clearance) |
| Pin 8 | VDDA β Output A supply with UVLO |
| Pin 9 | OUTA β Gate drive output A (4-A source / 6-A sink) |
| Pin 10 | GND β Output A ground return |
| Pin 11 | NC β No connect (isolation clearance) |
| Pin 12 | NC β No connect (isolation clearance) |
| Pin 13 | VDDB β Output B supply with UVLO |
| Pin 14 | OUTB β Gate drive output B (4-A source / 6-A sink) |
| Pin 15 | GNDB β Output B ground return |
| Pin 16 | NC β No connect |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this component. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
UCC21520Q-Q1 is suitable for 6 applications: Automotive Traction Inverter, Onboard Charger (OBC), Solar String Inverter, Industrial Motor Drives, High-Voltage DC-DC Converters, SiC Power Module Evaluation and Test Systems.
Automotive Traction Inverter
In traction inverters, the UCC21520Q-Q1 drives SiC MOSFET or IGBT half-bridge modules from a controller referenced to low-voltage chassis ground. Its 5.7-kVRMS reinforced isolation and minimum 125 V/ns CMTI survive the fast switching edges of 800-V SiC stages, while 4-A/6-A peak currents minimize switching losses that directly affect driving range. AEC-Q100 qualification supports the automotive quality flow required by OEMs. Place the driver close to the module gate terminals and use separate source return pins for each channel to limit loop inductance below 10 nH.
Recommended
Onboard Charger (OBC)
Automotive onboard chargers use PFC and LLC power stages at high voltage, requiring reinforced isolation between the digital controller and floating power switches. The UCC21520-Q1 provides 5.7-kVRMS reinforced isolation in a compact 16-SOIC, and its dual-input configuration fits both half-bridge PFC and LLC topologies. The 8-V UVLO ensures SiC MOSFETs are not driven with insufficient gate voltage, preventing operation in the resistive region. At 100-kHz+ LLC switching, the driver's low propagation delay and pulse-width distortion preserve duty-cycle accuracy for resonant control.
Recommended
Solar String Inverter
Solar string inverters drive IGBT or SiC half-bridges at 600 to 1500 V DC bus, where the UCC21520-Q1's reinforced isolation barrier meets grid-tied safety isolation requirements. High CMTI of at least 125 V/ns tolerates the dv/dt of fast power devices switching at 20 to 100 kHz, and the DIS pin allows safe shutdown during fault conditions detected by isolated sensing. The dual-channel architecture with interlock mode protects against shoot-through in half-bridge configurations, improving converter robustness in outdoor environments with wide temperature swings.
Recommended
Industrial Motor Drives
Three-phase industrial motor drives use six gate-drive channels for IGBT or SiC power modules; the UCC21520-Q1 drives two of these channels with 4-A/6-A peaks, reducing gate resistor sizing constraints and switching loss. Best-in-class pulse-width distortion keeps phase currents balanced, minimizing torque ripple. TTL/CMOS-compatible inputs connect directly to 3.3-V MCU PWM outputs without level translation. Its UVLO on both supply pins prevents under-driven gate operation during VDDA/VDDB power-up, a common cause of power device degradation in servo and factory automation drives.
Recommended
High-Voltage DC-DC Converters
Isolated DC-DC converters for 48-V to 400-V/800-V conversion use phase-shifted full-bridge or LLC topologies where the UCC21520-Q1 drives the primary-side bridges with reinforced isolation to the control side. Operation up to 5 MHz supports high-frequency designs that shrink magnetics, while low propagation delay enables tight phase-shift accuracy. The DIS pin supports fast system shutdown during overcurrent events detected within microseconds. Designers should provide a floating bias supply (for example, from UCC25800-Q1) for VDDB referenced to the switching node.
Recommended
SiC Power Module Evaluation and Test Systems
Double-pulse testers and SiC module characterization rigs need gate drivers that switch at high dv/dt without corruption from common-mode transients. The UCC21520-Q1's minimum 125 V/ns CMTI and 5.7-kVRMS isolation maintain signal integrity during high-speed switching tests up to 5 MHz, enabling accurate measurement of switching energy and reverse recovery. Independent channel control via INA/INB allows single-channel double-pulse sequences, while the DIS input provides a hardware-safe enable path. Flexible dead-time control via input timing supports characterization of gate resistor combinations.
Recommended
Recommended Products Summary
Engineering reference data for UCC21520Q-Q1 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | UCC21520 | UCC21521 | UCC21530 | UCC21550 | NCP51705 |
|---|---|---|---|---|---|---|
| Package | 16-SOIC wide-body (DWQ) | 16-SOIC (DW) - same | 16-SOIC (DW) - same | 16-SOIC (DW) - same | 16-SOIC (DW) | 16-SOIC |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | onsemi |
| Peak Source Current | 4 A | 4 A | 4 A | 4 A | 4 A | [DATA_NEEDED] |
| Peak Sink Current | 6 A | 6 A | 6 A | 6 A | 6 A | [DATA_NEEDED] |
| Isolation Rating | 5.7 kVRMS reinforced | 5.7 kVRMS | 5.7 kVRMS | 5.7 kVRMS | 5.7 kVRMS | [DATA_NEEDED] |
| CMTI | 125 V/ns min | 125 V/ns min | 125 V/ns min | 100 V/ns min | [DATA_NEEDED] | [DATA_NEEDED] |
| Control Pin | DIS (disable, active high) | DIS | EN (enable) | EN (enable) | [DATA_NEEDED] | [DATA_NEEDED] |
| Automotive AEC-Q100 | Yes (Q1) | No (standard grade) | Standard grade (Q1 variant exists) | Q1 variant available | [DATA_NEEDED] | [DATA_NEEDED] |
| Price (1 pc, as of 2026-08-29) | ~4.95 USD | lower (non-Q1) | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Automotive AEC-Q100 qualification (vs UCC21520)
- Higher CMTI than UCC21530 (vs UCC21530)
- Active-high disable pin (vs UCC21521)
Design Notes
Keep the gate-drive loop (OUT pin, gate resistor, gate, source return) as small as possible. The DWQ wide-body SOIC provides 8 mm of creepage between input and output sides - do not route any low-voltage signals through the isolation clearance zone. Place 0.1 uF + 10 uF decoupling capacitors within 2 mm of VDDA/VDDB pins and connect the driver ground return directly to the power device source or emitter Kelvin terminal.
Size the floating bias supply (VDDB) for at least the average gate-drive current: Qg x fsw per channel, plus driver quiescent current. For a SiC MOSFET with 60 nC gate charge at 100 kHz, budget roughly 6 mA per channel plus margin. Verify the VDDB rail stays above the 8-V UVLO threshold during transients, or outputs will be forced low and cause erratic switching.
The DIS pin is active-high and overrides both inputs - do not leave it floating; tie it to GND with a pulldown if unused. Input thresholds are TTL/CMOS compatible and independent of VCCI, but slow-rising PWM edges can cause output chatter; use a Schmidt buffer or ensure controller edge rates are fast. When replacing UCC21520 with UCC21521, note the control pin polarity is inverted (EN vs DIS).
Compliance Information
AEC-Q100 qualified per Q1 designation and TI datasheet title (Automotive). RoHS compliance per DigiKey listing.
