A42MX09-1PQG160M - 14K Gate MX FPGA, 160-PQFP | Microchip
MPN: A42MX09-1PQG160M ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $68.5 | $68.50 |
| 10 | $62.1 | $621.00 |
| 100 | $55.8 | $5,580.00 |
| 500 | $49.9 | $24,950.00 |
| 1,000 | $44.2 | $44,200.00 |
A42MX09-1PQG160M Overview
An FPGA (Field-Programmable Gate Array) is a semiconductor device containing a fabric of configurable logic blocks and programmable interconnects that the designer configures after manufacturing. Within the programmable logic hierarchy, the MX family sits under Actel/Microsemi antifuse FPGAs -> field-programmable gate arrays -> programmable logic ICs. Antifuse-based MX devices are one-time programmable, giving them inherent resistance to configuration corruption (SEU robustness) and instant-on behavior with no external configuration memory.
Key features include a flexible 5.0V-tolerant architecture, dual 3.3V/5V supply operation for legacy system integration, 14K system gates (684 logic cells per Microchip USA data), and a lead-free, RoHS-aligned 160-BQFP surface-mount package. The PQFP package with 0.65 mm terminal pitch (JESD-30 S-PQFP-G160) simplifies inspection and rework compared with fine-pitch BGAs.
The MX architecture combines combinational and sequential logic modules with rich local routing, providing predictable timing for glue logic consolidation, legacy PLD integration, and control-plane functions. The -1 speed grade supports clock frequencies up to the 148 MHz/247 MHz ratings noted in distributor and manufacturer data.
Typical applications include legacy design continuation for military/industrial systems, integration of multiple discrete PLDs into a single low-cost chip, bus interface and address decoding, and industrial control where 5V compatibility is still required.
Design consideration: because MX antifuse devices are one-time programmable, verify the full design in simulation and, where possible, prototype on a larger MX device before programming production units. Pricing referenced is as of 2026-08-30.
Drop-in alternatives for A42MX09-1PQG160M — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with A42MX09-1PQG160M (same form factor and footprint) — differing in Package, RoHS Status, Family, Configuration, System Gates.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
A42MX09-1PQG160
✅ Drop-In✓ In Stock
$20.6 / Unit
View Datasheet →A42MX09-3PQG160I
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$41.8 / Unit
View Datasheet →A42MX09-3PQG160
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$26.4 / Unit
View Datasheet →A42MX09-PQG160A
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$1 / Unit
View Datasheet →A42MX09-PQG160M
✅ Drop-In✓ In Stock
$29.8 / Unit
View Datasheet →A42MX16-1PQG160I
⚡ Same Package✓ In Stock
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View Datasheet →A42MX09-1PQG160M Maximum Ratings & Electrical Characteristics
| Family | MX (42MX) |
| System Gates | 14000 |
| Logic Cells | 336 |
| Total Logic Cells | 684 |
| User I/O | 101 |
| Max Toggle Rate | 148 MHz / 247 MHz |
| Process Technology | 0.45 um CMOS |
| Supply Voltage | 3.3 V / 5 V |
| Speed Grade | -1 |
| Package | 160-Pin PQFP (BQFP), 0.65 mm pitch |
| Mounting Type | Surface Mount |
| Programmable Type | Antifuse (one-time programmable) |
| Lead Free | Yes |
| Configuration | Single-chip, no external boot device required |
| RoHS Status | Lead-free per distributor listing |
A42MX09-1PQG160M Pin Configuration
| Pin 1 | IO — User I/O (bank assignment per datasheet pin table) |
| Pin [DATA_NEEDED] | VCC — Core/IO power supply, 3.3V or 5V per family datasheet |
| Pin [DATA_NEEDED] | GND — Ground |
| Pin [DATA_NEEDED] | TDI — JTAG boundary-scan test data in (chain starts at TDI) |
| Pin [DATA_NEEDED] | TDO — JTAG boundary-scan test data out (chain ends at TDO) |
| Pin [DATA_NEEDED] | TCK — JTAG test clock |
| Pin [DATA_NEEDED] | TMS — JTAG test mode select |
| Pin [DATA_NEEDED] | CLK — Dedicated clock input (per MX family pinout) |
Typical Applications
A42MX09-1PQG160M is suitable for 6 applications: Legacy Military System Sustainment, 5V Legacy Industrial Control, Single-Chip PLD Integration / ASIC Alternative, Bus Interface and Address Decoding, Avionics and High-Reliability Control Logic, Test and Measurement Fixtures.
Legacy Military System Sustainment
The A42MX09-1PQG160M's M-suffix qualification and antifuse one-time-programmable fabric make it well suited to maintaining fielded military electronics. The 14K-gate MX die integrates legacy PAL/GAL/PLD control logic into a single 160-PQFP chip, and 5V-tolerant I/O connects directly to older 5V bus architectures. Because there is no external configuration memory, the design is immune to configuration corruption in harsh environments, and the 0.65 mm-pitch PQFP supports depoting-level inspection and rework rather than BGA reflow.
Recommended
5V Legacy Industrial Control
Many industrial plants still run 5V logic rails; the A42MX09-1PQG160M accepts 3.3V or 5V supply per the MX family datasheet, eliminating level shifters. The 101 user I/O handle address decoding, sequencer, and interlock logic for PLC peripherals and motor-control panels. The 0.45 um antifuse process provides deterministic timing (148 MHz/247 MHz toggle ratings) without configuration boot delays, so I/O is active at power-up - valuable in safety interlock chains that must not wait for a configuration load.
Recommended
Single-Chip PLD Integration / ASIC Alternative
Microchip positions MX as a low-cost single-chip ASIC alternative for high-volume designs. Boards that previously used several 22V10-class PLDs or glue-logic 74-series devices can consolidate the functions into the 336-cell fabric of the A42MX09. Compared with an ASIC, the FPGA avoids mask NRE charges and allows design updates by programming a new device, while compared with SRAM FPGAs it removes the external configuration flash and its boot-failure risk, reducing total BOM cost in volume production.
Recommended
Bus Interface and Address Decoding
With 101 user I/O and dual 3.3V/5V supply, the A42MX09-1PQG160M directly terminates legacy microprocessor buses (e.g., 68000-family or 80x86 external buses) and implements chip-select, wait-state, and interrupt logic. The -1 speed grade's 148 MHz internal toggle capability comfortably meets sub-20 ns decoder access requirements typical of 25-40 MHz embedded CPUs. The VQG100/TQG176 family siblings allow footprint right-sizing, but the 160-pin PQFP maximizes available I/O for wide multiplexed buses.
Recommended
Avionics and High-Reliability Control Logic
Antifuse FPGAs are a standard choice in avionics control channels because the programmed interconnect cannot change under radiation-induced upset - no configuration scrubber is needed. The A42MX09-1PQG160M in the 160-PQFP provides 684 logic cells for ARINC/ MIL-STD-1553 interface glue, power-up sequencing, and built-in-test logic. The instant-on property means monitoring logic is alive before a processor finishes booting, and Microchip's long lifecycle support for the MX family suits programs with multi-decade sustainment obligations.
Recommended
Test and Measurement Fixtures
The A42MX09-1PQG160M is convenient in bed-of-nails and functional test fixtures where deterministic power-up state and 5V tolerance are needed to interface with devices under test from mixed logic generations. The 336-cell fabric implements protocol emulation, clock division, and signature capture; the 148 MHz toggle rating covers common test clocks. Because the antifuse programming is permanent, fixture configurations cannot drift or corrupt in production environments, and replacement devices can be pre-programmed as spares.
Recommended
Recommended Products Summary
Engineering reference data for A42MX09-1PQG160M — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | A42MX09-1PQG160 | A42MX09-3PQG160I | A42MX16-1PQG160I |
|---|---|---|---|---|
| Package | 160-PQFP (BQFP) | 160-PQFP - same | 160-PQFP - same | 160-PQFP - same |
| Brand | Microchip Technology (Microsemi) | Microchip Technology | Microchip Technology | Microchip Technology |
| System Gates | 14000 | 14000 | 14000 | 24000 |
| Speed Grade | -1 | -1 | -3 (faster) | -1 |
| Supply Voltage | 3.3 V / 5 V | 3.3 V / 5 V | 3.3 V / 5 V | 3.3 V / 5 V |
| Temperature Grade | M (extended/military) | standard (no M) | I (industrial) | I (industrial) |
Key Differentiators
- M-suffix extended qualification in 5V-tolerant antifuse fabric (vs A42MX09-1PQG160)
- Lower cost at equivalent logic when speed margin allows (vs A42MX09-3PQG160I)
- Same-footprint upward migration path (vs A42MX16-1PQG160I)
Design Notes
MX antifuse FPGAs are one-time programmable. Unlike SRAM FPGAs you cannot reflash a mis-programmed device - each programming attempt consumes a part. Complete full timing simulation and use a larger MX device (e.g., A42MX16) for prototyping where possible, then port to the A42MX09 for production. Budget spare devices at roughly 1.2x programmed quantity.
The MX family supports both 3.3V and 5V supplies; confirm which supply domain each I/O bank uses before routing the PCB. Mixing 5V legacy peripherals with 3.3V logic is safe on 5V-tolerant MX I/O, but verify per-pin ratings in the 40MX/42MX datasheet (DS2136/DS2316) rather than assuming blanket 5V tolerance across all banks.
The 160-pin PQFP uses 0.65 mm pitch with gull-wing leads. Use a standard QFP-160 land pattern with slightly extended toes for solder-joint inspection. Decouple each VCC pin with 0.1 uF ceramic capacitors placed within 3 mm of the pin, and add bulk 10 uF near the corners of the package to handle simultaneous switching noise on 101 I/O.
The JTAG boundary-scan chain runs from TDI to TDO and is useful for ICT fixture continuity testing on this PQFP. Plan TCK routing as a short star trace from the programming header, keep TMS/TCK away from switching I/O, and fit a 10K pull-up on TMS and TDI so the chain stays in a defined state when the header is unpopulated.
Compliance Information
Distributor listings describe A42MX09-1PQG160M as LEAD FREE. Formal RoHS/REACH certificates should be obtained from Microchip environmental documentation for this exact ordering code.
