A42MX09-3PQG160 - 14K Gate 5V FPGA 160-BQFP | Microchip
MPN: A42MX09-3PQG160 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $35.2 | $352.00 |
| 100 | $31.8 | $3,180.00 |
| 500 | $29.1 | $14,550.00 |
| 1,000 | $26.4 | $26,400.00 |
A42MX09-3PQG160 Overview
An FPGA (Field-Programmable Gate Array) is a semiconductor device containing a fabric of configurable logic blocks and programmable interconnects that the designer wires together post-manufacture. Within the programmable logic hierarchy, FPGAs sit above CPLDs and PLDs in capacity and flexibility, and the MX family is a single-chip, antifuse-style ASIC alternative specifically positioned for integrating legacy 5.0V PLD designs into one low-cost, high-volume device.
Key features include a 5.0V-tolerant architecture that directly interfaces with legacy 5V bus systems without level shifting, 684 CLBs of programmable logic, and speed-grade -3 timing supporting internal clock rates up to 268 MHz. The 101 available user I/O pins and the 160-BQFP package make the device well suited to through-hole-replacement and industrial retrofits where QFP soldering and 5V compatibility are required. The MX fabric offers deterministic, ASIC-like timing suited to high-volume, cost-sensitive production.
Architecturally, the MX family uses a flexible logic module approach with combinational and sequential modules, providing an efficient platform for state machines, glue logic consolidation, and legacy PLD migration. As a one-time-programmable single-chip solution, it removes configuration PROMs and improves reliability compared to SRAM-based FPGAs.
Typical applications include industrial control consolidation, legacy PLD integration, telecommunications line cards operating at 5V, military/industrial upgrade programs, and high-volume ASIC prototyping alternatives.
Design consideration: verify I/O allocation early, since the 101-user-I/O limit and fixed 160-BQFP pinout require pin planning before PCB layout; also confirm 5V supply integrity with adequate decoupling near all VCC pins.
Drop-in alternatives for A42MX09-3PQG160 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with A42MX09-3PQG160 (same form factor and footprint) — differing in RoHS Status, Family, Package, System Gates, Speed Grade.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
A42MX09-PQG160M
✅ Drop-In✓ In Stock
$29.8 / Unit
View Datasheet →A42MX09-3PQG160M
✅ Drop-In📋 Reference alternative (not in catalog)
A42MX16-2PQG160I
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$1 / Unit
View Datasheet →A42MX24-2PQG160I
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$44 / Unit
View Datasheet →A42MX09-3PQG160 Maximum Ratings & Electrical Characteristics
| Family | MX (Actel/Microsemi) |
| System Gates | 14000 |
| Configurable Logic Blocks (CLBs) | 684 |
| Number of I/Os | 101 |
| Supply Voltage | 5.0 V |
| Maximum Frequency | 268 MHz |
| Speed Grade | 3 |
| Programmable Type | Field Programmable Gate Array (FPGA) |
| Package | 160-BQFP |
| Mounting Type | Surface Mount |
| Technology | CMOS |
| Product Series | A42MX09 |
| Lead Free | Yes (LEAD FREE per distributor data) |
A42MX09-3PQG160 160-bqfp Pin Configuration Guide
Pin configuration for A42MX09-3PQG160 (160-bqfp package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for A42MX09-3PQG160.
Refer to the datasheet for full pin configuration.
Typical Applications
A42MX09-3PQG160 is suitable for 6 applications: Legacy PLD Integration, Industrial Control Systems, Telecommunications Line Cards, Military and Defense Upgrades, ASIC Prototyping Alternative, Test and Measurement Equipment.
Legacy PLD Integration
The A42MX09-3PQG160 consolidates multiple legacy 5V PLDs, GALs, and PALs into a single 14K-gate device, directly matching the 5.0V I/O levels of legacy buses without level shifters. With 684 CLBs and 101 user I/Os, typical multi-PLD glue-logic boards fit comfortably within the fabric. As a one-time-programmable single-chip solution it eliminates configuration PROMs and their boot-time dependencies, improving system reliability and reducing BOM count in high-volume industrial retrofits.
Recommended
Industrial Control Systems
In industrial controllers, the A42MX09-3PQG160 provides deterministic ASIC-like timing for state machines, interlocks, and motor sequencing logic at up to 268 MHz internal operation on a robust 5.0V rail common in factory environments. The 101 user I/Os interface directly with 5V sensors, relays, and optocoupler outputs. The 160-BQFP package is hand-solderable for service and rework, and the PQ160 footprint is shared with A42MX16/A42MX24 for future logic expansion without PCB redesign.
Recommended
Telecommunications Line Cards
5V-tolerant telecom backplanes and line cards benefit from the MX family's native 5.0V architecture, which connects directly to legacy E1/T1 framer and backplane signaling levels. The 268 MHz speed grade supports timing-critical framing and multiplexing logic, while 101 I/O pins handle address, data, and control buses. One-time programmability removes SRAM configuration overhead, ensuring the card is functional at power-up with no configuration controller or serial PROM required.
Recommended
Military and Defense Upgrades
The A42MX09-3PQG160M military variant and the PQG160M packaging options serve defense sustainment programs replacing obsolete bipolar PLDs. The MX family's single-chip, non-volatile nature and 5.0V tolerance match rack-level legacy power rails. With 14K gates and 684 CLBs, radar interface glue logic, bus arbiters, and test-point multiplexing consolidate reliably. The identical 160-BQFP footprint across military and industrial variants simplifies dual-source qualification within the same PCB layout.
Recommended
ASIC Prototyping Alternative
For low- to mid-volume ASIC replacements, the A42MX09-3PQG160 offers a one-time-programmable, single-chip ASIC alternative at 14K gates. Deterministic antifuse-style timing simplifies static timing analysis versus SRAM FPGAs, and the fixed 5.0V fabric matches the ASIC's original I/O environment. Designers implement the netlist once with Microchip/Microsemi Designer software and program via standard programmers, avoiding mask charges while keeping per-unit cost low at high volumes.
Recommended
Test and Measurement Equipment
Bench and ATE instruments use the A42MX09-3PQG160 for trigger logic, timing generators, and bus-interface glue logic where deterministic sub-microsecond response matters. The 5.0V fabric drives legacy instrument backplane signals directly with 101 I/Os, and 268 MHz speed-grade performance covers high-resolution counter and encoder interfaces. Its non-volatile configuration ensures the instrument powers up immediately with no boot latency, an important requirement for production test-floor equipment.
Recommended
Recommended Products Summary
Engineering reference data for A42MX09-3PQG160 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | A42MX09-PQG160M | A42MX09-3PQG160M | A42MX16-2PQG160I | A42MX24-2PQG160I |
|---|---|---|---|---|---|
| Package | 160-BQFP (PQ160) | 160-BQFP (PQ160) - same | 160-BQFP (PQ160) - same | 160-BQFP (PQ160) - same | 160-BQFP (PQ160) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| System Gates | 14000 | 14000 | 14000 | 16000-class | 24000-class |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
Key Differentiators
- Native 5.0V architecture (vs Modern low-voltage FPGAs)
- One-time-programmable single-chip operation (vs A42MX24-2PQG160I)
- Cost-optimized density point (vs A42MX16-2PQG160I)
Design Notes
The MX family operates on a single 5.0V rail. Decouple every VCC pin pair on the 160-BQFP with 0.1uF ceramic capacitors placed within 5 mm of the pin, plus at least 10uF of bulk capacitance per device. Because the fabric is one-time-programmable and draws current primarily during switching, estimate worst-case current from post-layout static timing simulation of the actual design rather than the family typical figure.
The 160-BQFP has 0.65mm-pitch leads; design land patterns per the Microchip MX datasheet packaging section. Allocate I/O early - only 101 of the 160 pins are user I/O, and the remaining pins are power, ground, and program/verify pins that must not be loaded during operation. Reserve the program-related pins with series resistors to allow in-system or bench programming access.
The A42MX09 is one-time-programmable: an incorrect fuse program cannot be erased, so always verify the design in simulation and on a development device before committing production units. Also remember the PQ160 footprint is shared with A42MX16 and A42MX24 - keep layout flexibility by routing spare fabric-routed I/O to test points, enabling a no-PCB-change density upgrade later.
Compliance Information
Distributor data (PCB Electronics Supply Chain) lists A42MX09-3PQG160 as LEAD FREE. Full RoHS/REACH certificate status should be confirmed with Microchip environmental documentation for this ordering code.
