IDTADC1207S080HW-C28 - 12-bit 80 MSPS Flash ADC | Renesas
MPN: IDTADC1207S080HW-C28 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.4 | $164.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.8 | $5,900.00 |
| 1,000 | $10.25 | $10,250.00 |
IDTADC1207S080HW-C28 Overview
A flash or pipelined ADC is a mixed-signal data converter that samples a continuous analog waveform at a fixed clock rate and produces parallel digital codes; pipelined architectures trade a few cycles of latency in favour of much lower power and smaller die area than a full flash design. The ADC1207S080 family is positioned for IF-sampling receivers, sitting in the hierarchy pipeline ADC -> ADC -> data converter -> data acquisition IC -> mixed-signal semiconductor, where its 80 MHz analog input allows direct digitisation of intermediate frequencies without an analog down-conversion stage.
Key features include 12-bit resolution, 80 MSPS maximum conversion rate, single 3.3 V supply operation, 1 Vp-p full-scale analog input, integrated track-and-hold amplifier, internal sample-and-hold clock driver, and an LVCMOS-compatible parallel digital interface. The 48-TQFP (7x7) package offers a 0.5 mm lead pitch suitable for standard SMT assembly lines and supports the -40C to +85C operating temperature range required for outdoor telecom infrastructure.
The architecture is built on a multi-stage pipeline with per-stage flash sub-ADC and digital error correction, achieving 12-bit linearity (DNL/INL within +/-1 LSB typical) while running at 80 MSPS. The wide analog input bandwidth enables direct sampling of IF frequencies up to 150 MHz, simplifying receiver design by eliminating an analog mixer stage and improving overall system linearity and cost.
Typical applications include multi-carrier GSM/UMTS/LTE base-station receivers, cable-headend digitisation, optical transport SONET/SDH line-card ADCs, and broadband test-and-measurement digitiser front-ends. The wide input bandwidth also suits radar IF, software-defined radio and digital oscilloscope front-end cards. The 450 mW dissipation at 80 MSPS allows forced-air or convection cooling in 1U/2U shelf designs without heatsinks.
When designing with this device, follow the recommended differential analog input drive with a 1 Vp-p full-scale range centred on a common-mode voltage of 1.65 V, and decouple AVDD/DVDD separately to minimise switching noise coupling into the analog front-end. For replacement scenarios, only the -C28 variant (Pb-free tape and reel, 2500 pcs) is drop-in compatible with this part number, while other speed grades in the ADC1207S family differ in maximum sampling rate and require re-qualification.
This page synthesises the manufacturer datasheet, distributor pricing as of 2026-10-13, drop-in alternative analysis, and practical RF/IF design notes not found on individual vendor listings.
Drop-in alternatives for IDTADC1207S080HW-C28 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with IDTADC1207S080HW-C28 (same form factor and footprint) — differing in Architecture, Package, Resolution, RoHS Status, Analog Supply Voltage.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
IDTADC1207S080HW-C18
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
IDTADC1206S040H-C18
✅ Drop-In✓ In Stock
$11.95 / Unit
View Datasheet →ADC1613S125HN-C1
✅ Drop-In✓ In Stock
$23.4 / Unit
View Datasheet →IDTADC1207S080HW-C28 Maximum Ratings & Electrical Characteristics
| Resolution | 12 bit |
| Number of Channels | 1 |
| Sampling Rate | 80 MSPS |
| Architecture | Pipelined Flash |
| Analog Input Bandwidth | 400 MHz (typical) |
| Full-Scale Input Range | 1 Vp-p |
| Analog Supply Voltage | 3.3 V |
| Digital Supply Voltage | 3.3 V |
| Power Dissipation | 450 mW (typical at 80 MSPS) |
| SNR | 72 dB at 30 MHz input |
| DNL | +/-1 LSB (typical) |
| INL | +/-1 LSB (typical) |
| Digital Interface | Parallel LVCMOS |
| Operating Temperature | -40C to +85C |
| Package | 48-TQFP (7x7 mm) |
| Lead Pitch | 0.5 mm |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
IDTADC1207S080HW-C28 Pin Configuration
| Pin 1 | AVDD — Analog 3.3 V supply |
| Pin 2 | AINP — Analog positive input |
| Pin 3 | AINN — Analog negative input |
| Pin 4 | AVSS — Analog ground |
| Pin 5 | VCM — Common-mode voltage output (1.65 V) |
| Pin 6 | REFIN — Reference input (decoupled) |
| Pin 7 | REFOUT — Internal reference output |
| Pin 8 | AVDD — Analog 3.3 V supply |
| Pin 9 | AVSS — Analog ground |
| Pin 10 | NC — Not connected (per datasheet) |
| Pin 11 | NC — Not connected (per datasheet) |
| Pin 12 | CLK — Sample clock input |
| Pin 13 | CLKN — Complementary sample clock input |
| Pin 14 | DVDD — Digital 3.3 V supply |
| Pin 15 | DVSS — Digital ground |
| Pin 16 | D11 — Digital output bit 11 (MSB) |
| Pin 17 | D10 — Digital output bit 10 |
| Pin 18 | D9 — Digital output bit 9 |
| Pin 19 | D8 — Digital output bit 8 |
| Pin 20 | D7 — Digital output bit 7 |
| Pin 21 | D6 — Digital output bit 6 |
| Pin 22 | D5 — Digital output bit 5 |
| Pin 23 | D4 — Digital output bit 4 |
| Pin 24 | DVDD — Digital 3.3 V supply |
| Pin 25 | DVSS — Digital ground |
| Pin 26 | D3 — Digital output bit 3 |
| Pin 27 | D2 — Digital output bit 2 |
| Pin 28 | D1 — Digital output bit 1 |
| Pin 29 | D0 — Digital output bit 0 (LSB) |
| Pin 30 | DRDY — Data ready output |
| Pin 31 | OE — Output enable (active low) |
| Pin 32 | MODE — Test mode select (tie low for normal operation) |
| Pin 33 | DVDD — Digital 3.3 V supply |
| Pin 34 | DVSS — Digital ground |
| Pin 35 | PD — Power-down (active high) |
| Pin 36 | AVDD — Analog 3.3 V supply |
| Pin 37 | AVSS — Analog ground |
| Pin 38 | NC — Not connected (per datasheet) |
| Pin 39 | NC — Not connected (per datasheet) |
| Pin 40 | VREF — Reference voltage decoupling |
| Pin 41 | FSADJ — Full-scale adjust input |
| Pin 42 | AVDD — Analog 3.3 V supply |
| Pin 43 | AVSS — Analog ground |
| Pin 44 | BIAS — Bias setting resistor |
| Pin 45 | AVDD — Analog 3.3 V supply |
| Pin 46 | AVSS — Analog ground |
| Pin 47 | AVDD — Analog 3.3 V supply |
| Pin 48 | AVSS — Analog ground |
Typical Applications
IDTADC1207S080HW-C28 is suitable for 6 applications: Multi-Carrier Cellular Base Station Receiver, Cable Headend QAM Digitiser, Optical Transport SONET/SDH Line-Card ADC, Broadband Test-and-Measurement Digitiser Front-End, Software-Defined Radio IF Sampling, Medical Ultrasound Receiver Front-End.
Multi-Carrier Cellular Base Station Receiver
The IDTADC1207S080HW-C28 is well suited to multi-carrier GSM/UMTS/LTE base-station receiver cards where several carriers must be digitised simultaneously. Its 80 MSPS sampling rate combined with 400 MHz analog input bandwidth allows direct IF sampling of carriers up to 150 MHz, eliminating an analog mixer stage and improving overall receiver linearity. With 72 dB SNR at 30 MHz input, the converter preserves the dynamic range required for multi-carrier power amplifiers and digital pre-distortion feedback paths. Place the ADC downstream of the RF front-end SAW filter, drive the analog input differentially at 1 Vp-p full-scale, and use separate AVDD/DVDD decoupling to keep digital switching noise out of the analog front-end.
Recommended
Cable Headend QAM Digitiser
Cable television headend equipment uses the IDTADC1207S080HW-C28 to digitise multiple QAM carriers directly at IF without analog down-conversion. The 80 MSPS sampling rate covers a typical 44 MHz QAM block plus adjacent channels, and the 12-bit resolution preserves the EVM margin required for 256-QAM and 1024-QAM downstream modulation. The wide 400 MHz analog input bandwidth lets the same ADC card digitise upstream (5-65 MHz) and downstream (54-1000 MHz) blocks when paired with an appropriate tuner. Use a differential balun driver with 1 Vp-p full-scale, and isolate the analog ground plane from the digital output bus to minimise digital feed-through.
Recommended
Optical Transport SONET/SDH Line-Card ADC
Optical transport line cards (SONET/SDH/OTN) use the IDTADC1207S080HW-C28 to digitise the analog error-correction feedback signal and overhead monitoring channels. The 12-bit resolution and 72 dB SNR provide the dynamic range required for accurate optical power monitoring and adaptive-equaliser feedback. The 80 MSPS rate oversamples the line-card data path sufficiently to feed a digital FIR equaliser and clock-data-recovery loop without aliasing. The 3.3 V single-supply operation simplifies power-tree design, and the 48-TQFP footprint is compatible with the lower-speed ADC1207S040 family, enabling one PCB layout to support multiple line rates.
Recommended
Broadband Test-and-Measurement Digitiser Front-End
Wide-bandwidth oscilloscope and spectrum-analyzer front-ends use the IDTADC1207S080HW-C28 as a single-channel IF digitiser in the second-stage down-converter path. Its 400 MHz analog input bandwidth supports digitisation of IF blocks up to 150 MHz without aliasing, and the 72 dB SNR preserves the spurious-free dynamic range needed for spectrum-analyzer residual-noise measurements. The 80 MSPS rate, paired with a digital FFT engine, achieves real-time spectrum analysis bandwidth exceeding 30 MHz, which is sufficient for general-purpose RF test instruments. The 48-TQFP package is footprint-compatible across the ADC1207S family, simplifying board reuse between 40 and 80 MSPS digitiser variants.
Recommended
Software-Defined Radio IF Sampling
Software-defined radio (SDR) platforms use the IDTADC1207S080HW-C28 to digitise the IF output of an analog front-end tuner, feeding the resulting sample stream to an FPGA or DSP for demodulation. Direct IF sampling eliminates one analog mixer and local-oscillator stage, reducing cost, phase noise, and spurious responses in the receiver. With 80 MSPS sampling and 400 MHz input bandwidth, the ADC captures the entire cellular, ISM, and public-safety bands after a single analog down-conversion to IF, enabling multi-mode multi-band operation in a single hardware platform. The LVCMOS parallel digital output feeds directly into FPGA LVCMOS receivers without requiring an external bus converter.
Recommended
Medical Ultrasound Receiver Front-End
Medical ultrasound beamformer front-ends use the IDTADC1207S080HW-C28 to digitise the received RF signal after the time-gain-control (TGC) amplifier. The 80 MSPS sampling rate is sufficient for ultrasound transducers operating up to 20 MHz, and the 12-bit resolution preserves the dynamic range required for harmonic imaging and contrast-agent detection. The wide analog input bandwidth allows the same ADC to support multiple transducer frequencies in a multi-modal cart, reducing the bill of materials. Low power dissipation (450 mW typical) keeps the per-channel thermal budget reasonable for dense array designs where many channels are placed in close proximity.
Recommended
Recommended Products Summary
Engineering reference data for IDTADC1207S080HW-C28 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | IDTADC1207S080HW-C18 | IDTADC1206S040H-C18 | ADC1613S125HN-C1 |
|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 48-TQFP (7x7 mm) | 48-TQFP (7x7 mm) - same | 48-TQFP (7x7 mm) - same | 48-TQFP (HVQFN-48) - same footprint family |
| Resolution | 12 bit | 12 bit | 12 bit | 16 bit |
| Sampling Rate | 80 MSPS | 80 MSPS | 40 MSPS | 125 MSPS |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Architecture | Pipelined Flash | Pipelined Flash | Pipelined Flash | Pipelined |
Key Differentiators
- Direct IF sampling capability up to 150 MHz without analog mixer (vs ADS8401IBPFBR)
- Pin-compatible lower-speed family member for cost-down designs (vs IDTADC1206S040H-C18)
- 12-bit IF-sampling performance optimised for telecom line cards (vs Generic 12-bit 80 MSPS ADCs)
Design Notes
Separate the analog and digital ground planes and join them only at a single point beneath the ADC's AVSS pins. Keep the analog input traces (AINP/AINN) as a 100-ohm differential pair, length-matched within 1 mm, and routed away from the parallel digital output bus (D0-D11). The sample clock (CLK/CLKN) should be routed as a 100-ohm differential pair and terminated close to the ADC. Place the 100 nF AVDD/DVDD decoupling capacitors within 5 mm of each supply pin, and add a 10 uF bulk capacitor at the board edge connector.
Use a low-noise LDO (such as a TPS7A4701) or a ferrite-bead filter to isolate the ADC's AVDD rail from digital switching noise. The 3.3 V analog supply should have measured ripple below 5 mVpp; any noise on AVDD couples directly into the analog input and degrades SNR. The DVDD rail can share the main 3.3 V digital plane but should still be locally decoupled at each pin. Estimated power budget: at 80 MSPS, the analog rail draws approximately 100 mA and the digital rail approximately 35 mA.
Drive the analog input differentially with a balun or a fully differential amplifier (such as an ADA4937) to achieve the specified 72 dB SNR at 30 MHz input. Single-ended drive halves the SNR and is not recommended. The common-mode voltage on AINP/AINN should be set to the VCM output (1.65 V) through 1 kohm resistors on each input leg. The sample clock duty cycle should be held at 50% +/-5%; an asymmetric clock generates harmonic distortion that cannot be calibrated out.
Do not leave the PD (power-down) pin floating; tie it low through a 10 kohm resistor for normal operation. The MODE pin must be tied low to disable the factory test mode. The OE pin enables the digital output bus and should be tied low for continuous output mode. The reference decoupling capacitor on VREF must be a 100 nF ceramic with ESR below 50 milliohm; a poor reference decoupling degrades linearity across temperature.
Compliance Information
RoHS-compliant Pb-free finish per the -C28 suffix; Renesas/IDT product identification. Not AEC-Q100 qualified (telecom-grade, not automotive). REACH compliance per Renesas product statement.
