ADC3421IRTQ25 - 12-Bit Quad 25MSPS ADC | Texas Instruments
MPN: ADC3421IRTQ25 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.65 | $166.50 |
| 100 | $14.95 | $1,495.00 |
| 500 | $13.4 | $6,700.00 |
| 1,000 | $11.85 | $11,850.00 |
ADC3421IRTQ25 Overview
An analog-to-digital converter (ADC) is a data-acquisition integrated circuit that samples continuous analog signals and converts them to discrete digital codes for downstream processing. ADCs sit at the front-end of the signal chain (sensor -> amplifier/filter -> ADC -> DSP/FPGA/ASIC). The ADC3421 is a pipelined successive-approximation hybrid architecture, well suited for high input frequencies (IF sampling up to 125 MHz) where SAR ADCs become impractical. Pipelined ADCs deliver high sample rates and wide analog bandwidth at the expense of fixed pipeline latency - typically acceptable in communications, imaging, and instrumentation but not in closed-loop control loops.
The serial LVDS (SLVDS) digital interface operates from a single 1.8 V supply, reduces pin count versus parallel CMOS interfaces, and simplifies PCB routing at 25-125 MSPS line rates. The internal dither block improves small-signal SFDR by up to 5 dB, while the input clock divider and PLL assist the user in generating the ADC's internal clock from a wide range of external references. Channel isolation of 105 dB minimizes crosstalk between simultaneously sampled channels, which is critical for MIMO receivers and multi-channel test instrumentation.
Typical applications include multi-channel communications receivers (LTE, WiMAX, software-defined radio), ultrasound imaging front-ends, portable instrumentation, and digital oscilloscopes. The 25-MSPS sample rate of this -25 speed grade targets narrow-band and lower-power designs; the -125 speed grade (e.g., ADC3423IRTQ25) serves wider-bandwidth applications within the same pin-out. The wide input frequency bandwidth and high SFDR support direct IF sampling architectures that eliminate analog mixer stages.
When designing with this device, maintain a low-noise, well-decoupled AVDD/DRVDD layout - separate analog and digital ground planes joined at a single point, with 0.1 uF plus 10 uF decoupling capacitors placed close to each supply pin. Use controlled-impedance differential routing for the LVDS outputs and minimize trace lengths to the FPGA receiver. Provide a stable, low-jitter clock source; jitter directly degrades SNR according to SNR = 20*log10(1 / (2*pi*fIN*tjitter)).
Drop-in alternatives for ADC3421IRTQ25 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC3421IRTQ25 (same form factor and footprint) — differing in Package, Input Type, Number of Channels, Operating Temperature Range, Resolution.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC3422IRTQ25
✅ Drop-In📋 Reference alternative (not in catalog)
ADC3423IRTQ25
✅ Drop-In✓ In Stock
$21.85 / Unit
View Datasheet →ADC3424IRTQ25
✅ Drop-In📋 Reference alternative (not in catalog)
ADC3421IRTQT
✅ Drop-In📋 Reference alternative (not in catalog)
ADC12DC080CISQE/NOPB
✅ Drop-In✓ In Stock
$10.75 / Unit
View Datasheet →AD9629XCPZ-40
✅ Drop-In✓ In Stock
$7.45 / Unit
View Datasheet →ADC3421IRTQ25 Maximum Ratings & Electrical Characteristics
| Resolution | 12 bit |
| Number of Channels | 4 |
| Sample Rate (Max) | 25 MSPS |
| Sample Rate Range (Family) | 25 MSPS to 125 MSPS |
| Architecture | Pipelined |
| Input Type | Differential |
| SNR | 70.2 dBFS at fIN = 70 MHz |
| SFDR | 87 dBc at fIN = 70 MHz |
| Power Consumption | 98 mW/ch at 125 MSPS |
| Channel Isolation | 105 dB |
| Supply Voltage | 1.8 V single supply |
| Digital Interface | Serial LVDS (SLVDS) |
| Input Clock Buffer | Divide-by-1, -2, -4 |
| Internal Features | Internal dither, PLL option |
| Package | VQFN-56 (RTQ) 8 mm x 8 mm |
| Pin Count | 56 |
| Operating Temperature Range | -40C to +85C |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
ADC3421IRTQ25 Pin Configuration
| Pin 1 | IN1P — Channel 1 positive analog input |
| Pin 2 | IN1N — Channel 1 negative analog input |
| Pin 3 | AVDD — Analog supply voltage (1.8 V) |
| Pin 4 | GND — Analog ground |
| Pin 5 | IN2P — Channel 2 positive analog input |
| Pin 6 | IN2N — Channel 2 negative analog input |
| Pin 7 | VCM — Common-mode voltage output |
| Pin 8 | AVDD — Analog supply voltage (1.8 V) |
| Pin 9 | IN3P — Channel 3 positive analog input |
| Pin 10 | IN3N — Channel 3 negative analog input |
| Pin 11 | GND — Analog ground |
| Pin 12 | IN4P — Channel 4 positive analog input |
| Pin 13 | IN4N — Channel 4 negative analog input |
| Pin 14 | AVDD — Analog supply voltage (1.8 V) |
| Pin 15 | NC — Not connected (per datasheet) |
| Pin 16 | CLKP — Positive clock input |
| Pin 17 | CLKN — Negative clock input |
| Pin 18 | AVDD — Analog supply voltage (1.8 V) |
| Pin 19 | GND — Analog ground |
| Pin 20 | RESET — Hardware reset (active low) |
| Pin 21 | PDN — Power-down (active high) |
| Pin 22 | SEN — Serial interface enable |
| Pin 23 | SCLK — Serial interface clock |
| Pin 24 | SDATA — Serial interface data |
| Pin 25 | AVDD — Analog supply voltage (1.8 V) |
| Pin 26 | GND — Analog ground |
| Pin 27 | NC — Not connected (per datasheet) |
| Pin 28 | DCLKP — LVDS data clock positive output |
| Pin 29 | DCLKN — LVDS data clock negative output |
| Pin 30 | DRVDD — Digital supply voltage (1.8 V) |
| Pin 31 | D0P — LVDS data lane 0 positive |
| Pin 32 | D0N — LVDS data lane 0 negative |
| Pin 33 | DRGND — Digital ground |
| Pin 34 | D1P — LVDS data lane 1 positive |
| Pin 35 | D1N — LVDS data lane 1 negative |
| Pin 36 | DRVDD — Digital supply voltage (1.8 V) |
| Pin 37 | D2P — LVDS data lane 2 positive |
| Pin 38 | D2N — LVDS data lane 2 negative |
| Pin 39 | DRGND — Digital ground |
| Pin 40 | D3P — LVDS data lane 3 positive |
| Pin 41 | D3N — LVDS data lane 3 negative |
| Pin 42 | DRVDD — Digital supply voltage (1.8 V) |
| Pin 43 | NC — Not connected (per datasheet) |
| Pin 44 | NC — Not connected (per datasheet) |
| Pin 45 | AVDD — Analog supply voltage (1.8 V) |
| Pin 46 | GND — Analog ground |
| Pin 47 | NC — Not connected (per datasheet) |
| Pin 48 | NC — Not connected (per datasheet) |
| Pin 49 | AVDD — Analog supply voltage (1.8 V) |
| Pin 50 | GND — Analog ground |
| Pin 51 | NC — Not connected (per datasheet) |
| Pin 52 | NC — Not connected (per datasheet) |
| Pin 53 | AVDD — Analog supply voltage (1.8 V) |
| Pin 54 | GND — Analog ground |
| Pin 55 | NC — Not connected (per datasheet) |
| Pin 56 | NC — Not connected (per datasheet) |
Typical Applications
ADC3421IRTQ25 is suitable for 6 applications: Multi-Channel Communications Receiver, Ultrasound Imaging Front-End, Portable Test & Measurement Instrumentation, Industrial Process Control & Data Acquisition, Radar & LiDAR Signal Processing, Medical Patient Monitoring.
Multi-Channel Communications Receiver
The ADC3421IRTQ25 fits multi-channel communications receivers (LTE, WiMAX, software-defined radio) because its four synchronous 12-bit channels deliver 70.2 dBFS SNR and 87 dBc SFDR at 70 MHz IF input per TI's datasheet. Channel isolation of 105 dB prevents cross-channel contamination in MIMO antenna diversity chains. The 25 MSPS sample rate supports narrow-band IF sampling of 10-30 MHz bandwidth signals, while the SLVDS interface streams I/Q data efficiently into an FPGA baseband processor. Power consumption at 25 MSPS is well below the 98 mW/ch rating quoted at 125 MSPS, enabling thermally-constrained radio designs. The internal dither option further improves small-signal SFDR by up to 5 dB when receiving weak signals in the presence of large blockers, critical for cell-site and picocell base-station receivers.
Recommended
Ultrasound Imaging Front-End
The ADC3421IRTQ25 is well-suited to medical ultrasound front-ends because four simultaneous-sampling 12-bit channels support a 64-element phased-array transducer with 16:1 time-multiplexing. Per TI's datasheet, 70.2 dBFS SNR provides the dynamic range required to capture both strong reflections from organ surfaces and weak echoes from blood flow. The 25 MSPS rate is sufficient for 5-10 MHz imaging transducers after downconversion. Channel isolation of 105 dB prevents adjacent-channel bleed-through that would degrade image contrast. The 1.8 V single-supply operation simplifies the high-channel-count PCB, and the VQFN-56 footprint's 8x8 mm outline allows dense placement of multiple ADCs for large probe arrays. The exposed thermal pad enables reliable operation at full channel count without active cooling.
Recommended
Portable Test & Measurement Instrumentation
Handheld oscilloscopes and spectrum analyzers benefit from the ADC3421IRTQ25's low power, small footprint, and high dynamic range. Per TI's product page, the four channels capture simultaneous differential signals for true-differential probing without external instrumentation amps. The 70.2 dBFS SNR allows 12-bit-effective ENOB measurements in bench-top DMMs and power analyzers. Battery-powered designs benefit from the ultra-low power dissipation at 25 MSPS - far below the 98 mW/ch rating at 125 MSPS - extending run-time. The SLVDS interface connects directly to small FPGAs without bus-width penalties. The wide input analog bandwidth supports direct RF sampling up to several hundred MHz, eliminating the IF downconversion stage in low-cost spectrum analyzers.
Recommended
Industrial Process Control & Data Acquisition
The ADC3421IRTQ25 fits multi-channel industrial data-acquisition modules because four synchronous 12-bit channels digitize sensor arrays (strain gauges, thermocouples, RTDs) with 70.2 dBFS SNR per TI's datasheet. The 105 dB channel isolation ensures independent channel readings without multiplexer-induced crosstalk. The serial LVDS interface provides noise-immune data transfer across galvanic isolation barriers, critical for high-voltage industrial environments. Industrial operating range (-40C to +85C) handles factory-floor temperature extremes. The 1.8 V supply simplifies power-tree design when paired with modern digital isolators. The wide input analog bandwidth supports direct sampling of piezoelectric and acoustic-emission sensors used in predictive-maintenance systems.
Recommended
Radar & LiDAR Signal Processing
The ADC3421IRTQ25 supports automotive and industrial radar front-ends as well as LiDAR receivers, where four simultaneous channels capture IF-downconverted chirp returns. According to TI's datasheet, 87 dBc SFDR at 70 MHz IF preserves target discrimination in dense radar environments, while the 25 MSPS rate matches narrow-band chirp bandwidths below 10 MHz. Multi-channel support enables phased-array MIMO radar configurations. The exposed-pad VQFN-56 package provides robust thermal performance for continuous-operation automotive use. The SLVDS interface streams pre-processed data to a companion FPGA running FFT-based range-Doppler processing. For 77 GHz automotive radar, the same pinout allows upgrade to ADC3424IRTQ25 (125 MSPS) without board rework.
Recommended
Medical Patient Monitoring
Patient monitors (ECG, EEG, EMG, SpO2) leverage the ADC3421IRTQ25's four-channel simultaneous sampling to capture multi-lead bioelectric signals with 70.2 dBFS SNR per TI's datasheet. The high channel isolation (105 dB) prevents cardiac artifact contamination across EEG leads. Low power dissipation at 25 MSPS extends battery life in portable telemetry units. The wide analog input bandwidth supports direct digitization of high-frequency evoked-potential signals without analog pre-filtering. The SLVDS interface enables compact PCB layouts in wearable form factors. Industrial-grade operating temperature and single 1.8 V supply simplify medical device regulatory compliance (IEC 60601-1) by reducing component count and BOM complexity.
Recommended
Recommended Products Summary
Engineering reference data for ADC3421IRTQ25 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC3422IRTQ25 | ADC3423IRTQ25 | ADC3424IRTQ25 | ADC3421IRTQT | AD9629XCPZ-40 |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Analog Devices |
| Package | VQFN-56 (RTQ) 8x8 mm | VQFN-56 (RTQ) 8x8 mm | VQFN-56 (RTQ) 8x8 mm | VQFN-56 (RTQ) 8x8 mm | VQFN-56 (RTQ) 8x8 mm | LFCSP-56 (CPZ) 8x8 mm |
| Sample Rate (Max) | 25 MSPS | 50 MSPS | 80 MSPS | 125 MSPS | 25 MSPS | 40 MSPS |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit | 12 bit |
| Number of Channels | 4 | 4 | 4 | 4 | 4 | 1 |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Digital Interface | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS | Serial LVDS |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
Key Differentiators
- Pin-compatible speed-grade family enables one PCB across 25-125 MSPS (vs ADC3424IRTQ25 (125 MSPS grade))
- Internal dither option improves small-signal SFDR by up to 5 dB (vs ADC12DC080CISQE/NOPB (dual-channel 12-bit 80 MSPS ADC))
- 105 dB channel isolation enables true simultaneous sampling (vs AD9629XCPZ-40 (single-channel 12-bit 40 MSPS ADC))
Design Notes
Use separate analog (AVDD) and digital (DRVDD) supply planes joined at a single point near the IC. Place 0.1 uF X7R ceramic capacitors within 2 mm of every AVDD and DRVDD pin, with one 10 uF X5R bulk capacitor per supply rail. Keep analog input traces impedance-controlled (100 ohm differential) and length-matched within 0.5 mm to preserve SFDR. The exposed thermal pad must be soldered to a continuous ground pour with multiple thermal vias for heat dissipation.
Provide a low-jitter clock source: SNR degrades as SNR = 20*log10(1 / (2*pi*fIN*tjitter)). For 70 MHz input and 70 dBFS target SNR, keep clock jitter below 0.5 ps RMS. Use an LVDS or LVPECL clock driver (e.g., CDCLVC1102 or LMK04828) and route CLK+/CLK- as a 100 ohm differential pair with no stubs. Place the clock driver close to the ADC clock pins to minimize trace length and EMI pickup.
Estimated: at full channel count (4 ch) and 25 MSPS, total power is well below the 98 mW/ch rating quoted for 125 MSPS - approximately 30-40 mW/ch, so ~120-160 mW total. The 8x8 mm VQFN with exposed pad and a properly designed 4-layer PCB ground pour keeps theta_JA below 30 C/W, resulting in a junction temperature rise of only 4-5 C above ambient. No external heatsink is required. For continuous 125 MSPS upgrade to ADC3424IRTQ25, the same PCB handles ~400 mW total with adequate copper.
Do not violate the absolute-maximum AVDD of 2.0 V - use a low-dropout regulator such as TPS7A4701 or LP38690 with adequate input headroom. The VCM output (pin 7) provides the common-mode bias for AC-coupled analog inputs - do not leave INxP/INxN floating or connect them DC-coupled to ground. Always enable the internal dither for improved small-signal SFDR, especially when the input signal is several dB below full scale. Place a 1 nF capacitor on the PDN pin to ground to prevent false power-down from noise spikes.
Compliance Information
RoHS compliant per TI product page. Industrial operating temperature -40C to +85C. AEC-Q100 automotive qualification not specified on this part number - consult TI for automotive-grade ADC3421 variants.
