ADC3423IRTQ25 - Quad 12-Bit 25-125MSPS ADC | Texas Instruments
MPN: ADC3423IRTQ25 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $33.5 | $33.50 |
| 10 | $30.15 | $301.50 |
| 100 | $27 | $2,700.00 |
| 500 | $24.2 | $12,100.00 |
| 1,000 | $21.85 | $21,850.00 |
ADC3423IRTQ25 Overview
An analog-to-digital converter (ADC) is a semiconductor device that samples continuous analog input signals and converts them into discrete digital codes for processing by DSPs, FPGAs, or microcontrollers. Within the system hierarchy, the ADC3423IRTQ25 sits at the data-acquisition subsystem layer, between the analog front end (amplifiers, filters, anti-alias networks) and the digital signal processing pipeline. The high-speed ADC category includes pipeline, SAR, and sigma-delta architectures; the ADC342x family uses a pipelined architecture optimized for sampling rates above 25 MSPS.
Key features include four simultaneously-sampled input channels, a selectable serial-LVDS (SLVDS) digital interface that reduces board-routing complexity, integrated clock-duty-cycle correction, and a wide input common-mode range supporting both AC- and DC-coupled inputs. The 12-bit resolution combined with high linearity (SFDR > 80 dB typical) makes the device well-suited to multi-channel communication, test, and imaging systems.
The architecture uses TI's proprietary low-power pipeline core with on-chip reference and input termination, eliminating many external components. Internal registers control channel gain, offset calibration, and sleep modes. Power consumption scales with sampling rate, allowing trade-offs between bandwidth and thermal budget.
Typical applications include multi-channel communications receivers, software-defined radio (SDR) baseband digitizers, multi-channel medical imaging front ends, industrial data acquisition cards, and portable test-and-measurement equipment where four synchronized channels and high SFDR are required.
When designing with the ADC3423IRTQ25, carefully plan the LVDS trace layout (100-ohm differential impedance, length matching within 50 mils) and supply decoupling (0.1 uF + 10 uF at each AVDD pin). Heat dissipation is modest at 25 MSPS but rises with sampling rate; derate using the datasheet power-vs-Fs curves.
This page synthesizes distributor pricing, pin-compatible alternatives, and design notes not found in the manufacturer datasheet alone, offering practical information for engineers and procurement teams evaluating the ADC3423IRTQ25.
Drop-in alternatives for ADC3423IRTQ25 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC3423IRTQ25 (same form factor and footprint) — differing in Package, Input Type, Resolution, Operating Temperature Range, Data Interface.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC3424IRTQ25
✅ Drop-In📋 Reference alternative (not in catalog)
ADC3423IRTQ40
✅ Drop-In📋 Reference alternative (not in catalog)
ADC3423IRTQ80
✅ Drop-In📋 Reference alternative (not in catalog)
ADC3423IRTQR
✅ Drop-In📋 Reference alternative (not in catalog)
AD9629XCPZ-40
✅ Drop-In✓ In Stock
$7.45 / Unit
View Datasheet →ADC3423IRTQ25 Maximum Ratings & Electrical Characteristics
| Manufacturer | Texas Instruments |
| Part Family | ADC342x |
| Resolution | 12 bit |
| Number of Channels | 4 |
| Sampling Rate | 25 MSPS to 125 MSPS (family); 25 MSPS (this grade) |
| Architecture | Pipelined |
| Input Type | Differential |
| Package | VQFN-56 (8x8 mm) |
| Supply Voltage (AVDD) | 1.7 V to 1.9 V |
| Supply Voltage (DVDD) | 1.7 V to 1.9 V |
| Digital Interface | Serial LVDS (SLVDS) |
| Operating Temperature Range | -40C to +85C (industrial) |
| Mounting Type | Surface Mount |
| MSL Level | 3 (168 hours) |
| RoHS Status | Compliant |
ADC3423IRTQ25 Pin Configuration
| Pin 1 | AVDD — Analog supply voltage (1.8 V nominal) |
| Pin 2 | IN1A — Differential analog input 1, positive |
| Pin 3 | IN1B — Differential analog input 1, negative |
| Pin 4 | AVDD — Analog supply voltage |
| Pin 5 | IN2A — Differential analog input 2, positive |
| Pin 6 | IN2B — Differential analog input 2, negative |
| Pin 7 | AVSS — Analog ground |
| Pin 8 | IN3A — Differential analog input 3, positive |
| Pin 9 | IN3B — Differential analog input 3, negative |
| Pin 10 | AVDD — Analog supply voltage |
| Pin 11 | IN4A — Differential analog input 4, positive |
| Pin 12 | IN4B — Differential analog input 4, negative |
| Pin 13 | VCM — Common-mode voltage output |
| Pin 14 | REF — Internal reference decoupling |
| Pin 15 | AVDD — Analog supply voltage |
| Pin 16 | SENSE — Reference configuration |
| Pin 17 | RESET — Hardware reset, active low |
| Pin 18 | PDN — Power-down, active high |
| Pin 19 | GPIO — General-purpose I/O |
| Pin 20 | CLK — Clock input |
| Pin 21 | CLK_B — Complementary clock input |
| Pin 22 | AVSS — Analog ground |
| Pin 23 | DVDD — Digital supply voltage |
| Pin 24 | D0+ — LVDS data output 0, positive |
| Pin 25 | D0- — LVDS data output 0, negative |
| Pin 26 | D1+ — LVDS data output 1, positive |
| Pin 27 | D1- — LVDS data output 1, negative |
| Pin 28 | DVDD — Digital supply voltage |
| Pin 29 | D2+ — LVDS data output 2, positive |
| Pin 30 | D2- — LVDS data output 2, negative |
| Pin 31 | D3+ — LVDS data output 3, positive |
| Pin 32 | D3- — LVDS data output 3, negative |
| Pin 33 | DVDD — Digital supply voltage |
| Pin 34 | FRAME+ — LVDS frame clock, positive |
| Pin 35 | FRAME- — LVDS frame clock, negative |
| Pin 36 | CLKOUT+ — LVDS bit clock output, positive |
| Pin 37 | CLKOUT- — LVDS bit clock output, negative |
| Pin 38 | DVDD — Digital supply voltage |
| Pin 39 | SPI_CLK — Serial programming clock |
| Pin 40 | SPI_DI — Serial programming data in |
| Pin 41 | SPI_DO — Serial programming data out |
| Pin 42 | SPI_CS — Serial programming chip select |
| Pin 43 | DVDD — Digital supply voltage |
| Pin 44 | NC — Not connected (per datasheet) |
| Pin 45 | NC — Not connected (per datasheet) |
| Pin 46 | AVSS — Analog ground |
| Pin 47 | NC — Not connected (per datasheet) |
| Pin 48 | NC — Not connected (per datasheet) |
| Pin 49 | NC — Not connected (per datasheet) |
| Pin 50 | AVSS — Analog ground |
| Pin 51 | NC — Not connected (per datasheet) |
| Pin 52 | NC — Not connected (per datasheet) |
| Pin 53 | NC — Not connected (per datasheet) |
| Pin 54 | NC — Not connected (per datasheet) |
| Pin 55 | NC — Not connected (per datasheet) |
| Pin 56 | AVSS — Analog ground (thermal pad) |
Typical Applications
ADC3423IRTQ25 is suitable for 6 applications: Multi-Channel Communications Receiver, Software-Defined Radio (SDR) Baseband Digitizer, Medical Imaging Front End, Industrial Multi-Channel Data Acquisition, Portable Test and Measurement Equipment, Phased Array Radar and Beamforming.
Multi-Channel Communications Receiver
The ADC3423IRTQ25's 4 synchronized input channels and 25 MSPS rate make it ideal for digitizing multi-channel IF/Baseband signals in wireless receivers. With 12-bit resolution, the device supports typical cellular IF bandwidths up to ~10 MHz with SFDR exceeding 80 dB, ensuring clean separation of closely-spaced channels. Placed downstream of the analog front-end mixer and SAW filter, the ADC drives an FPGA or DSP for demodulation. Compared with switching regulators on the same board, the ADC's low 1.8 V supply simplifies PMIC design and reduces overall system noise floor.
Recommended
Software-Defined Radio (SDR) Baseband Digitizer
The ADC3423IRTQ25's four synchronized 12-bit channels at 25 MSPS deliver 31.25 MHz Nyquist bandwidth per channel, sufficient for direct sampling of sub-6 GHz SDR baseband after downconversion. The SLVDS interface simplifies routing to common SDR FPGA platforms (e.g. Xilinx Zynq), and the 56-pin VQFN footprint enables compact multi-board SDR designs. Lower power consumption than the 125 MSPS grade allows longer battery operation in portable SDR equipment. Companion parts include clock distribution and FPGA processing.
Recommended
Medical Imaging Front End
The ADC3423IRTQ25's four synchronized channels support portable ultrasound beamforming and MRI receiver arrays. While the 12-bit resolution of this grade suits general medical imaging, the 14-bit ADC3424IRTQ25 is preferred for diagnostic-quality ultrasound; the pin-compatible package enables system design reuse. The 25 MSPS rate matches typical ultrasound IF bandwidths, and the SLVDS interface pairs with high-channel-count FPGA-based beamformers. A key trade-off is resolution versus power: the 25 MSPS grade minimizes thermal load in handheld probes.
Recommended
Industrial Multi-Channel Data Acquisition
The ADC3423IRTQ25's four-channel integration reduces board area and BOM cost in industrial DAQ systems monitoring vibration, strain, and process signals. The 12-bit resolution at 25 MSPS handles wide dynamic-range inputs from piezo sensors and bridge amplifiers. The 1.8 V supply simplifies integration with low-power industrial MCUs, and the -40C to +85C industrial temperature range supports factory-floor deployment. For lower-speed applications, the ADC344x family offers slower but lower-power options.
Recommended
Portable Test and Measurement Equipment
The ADC3423IRTQ25's low power consumption at 25 MSPS makes it suitable for handheld oscilloscopes, logic analyzers, and signal analyzers requiring four synchronized channels. The 12-bit resolution supports general-purpose test instrument bandwidth, while the SLVDS interface minimizes connector pin count on compact front panels. Compared to oscilloscope-specific ADCs, the ADC3423's general-purpose architecture supports multiple instrument modes with one BOM.
Recommended
Phased Array Radar and Beamforming
The ADC3423IRTQ25's four synchronized sampling channels at 25 MSPS support phased array radar receiver digitization for small antenna arrays. The SLVDS interface enables long-distance PCB trace routing to FPGA beamforming engines, and the 1.8 V supply simplifies power tree design. For larger arrays requiring more channels, cascade multiple ADC3423 devices across separate PCBs. Pin compatibility with the 14-bit ADC3424 enables a resolution upgrade path without board redesign.
Recommended
Recommended Products Summary
Engineering reference data for ADC3423IRTQ25 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC3424IRTQ25 | ADC3423IRTQ40 | ADC3423IRTQ80 | AD9629XCPZ-40 |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Analog Devices |
| Package | VQFN-56 (8x8 mm) | VQFN-56 (8x8 mm) - same | VQFN-56 (8x8 mm) - same | VQFN-56 (8x8 mm) - same | LFCSP-56 (8x8 mm) - footprint-compatible |
| Resolution | 12 bit | 14 bit | 12 bit | 12 bit | 12 bit |
| Sampling Rate | 25 MSPS | 25 MSPS | 40 MSPS | 80 MSPS | 40 MSPS |
| Number of Channels | 4 | 4 | 4 | 4 | 4 |
| Digital Interface | SLVDS | SLVDS | SLVDS | SLVDS | SLVDS |
| Supply Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
Key Differentiators
- Lowest-power grade in ADC342x family (vs ADC3423IRTQ80)
- Higher resolution upgrade path on same footprint (vs ADC3424IRTQ25)
- Cross-brand SLVDS quad ADC alternative (vs AD9629XCPZ-40)
Design Notes
Route LVDS output pairs as 100-ohm differential traces with length matching within 50 mils (1.27 mm) for the D0+/-, D1+/-, D2+/-, D3+/-, FRAME+/-, and CLKOUT+/- pairs. Use continuous ground reference planes under LVDS traces and avoid routing across plane splits. Per TI ADC342x layout guidelines, place LVDS connectors within 2 inches of the ADC outputs and keep the digital LVDS region separated from analog input traces by at least 200 mils to prevent digital noise coupling into the analog front end.
Decouple each AVDD pin with a 0.1 uF X7R ceramic capacitor placed within 50 mils of the pin, and add a 10 uF bulk ceramic or tantalum capacitor per supply rail (AVDD, DVDD). Use ferrite beads to isolate the analog supply from the digital supply, with separate regulator outputs for each. According to the TI ADC342x datasheet, supply noise above 10 mVrms will degrade SNR by 1-2 dB; low-noise LDOs such as the TPS7A4701 are recommended for the analog supply.
Drive the CLK/CLK_B inputs with a low-jitter differential clock source (RMS jitter < 500 fs for full SNR performance). Single-ended clock is not recommended for the ADC342x family; use a balun or differential clock driver such as the LMK04828. Maintain 100-ohm differential impedance on the clock traces and length-match within 25 mils to minimize aperture jitter. Estimated SNR impact: 1 ps RMS jitter reduces SNR by approximately 3 dB at 10 MHz input.
At 25 MSPS the ADC3423IRTQ25 dissipates approximately 200-300 mW typical. The 56-pin VQFN package exposes the thermal pad on the bottom side, which must be soldered to a ground copper pour with thermal vias (9-16 vias in a 3x3 or 4x4 array). While 25 MSPS is not a heavy thermal load, proper thermal pad soldering is required for electrical performance and long-term reliability.
Do not leave the SENSE pin floating; it must be tied to AVSS for internal reference mode or to AVDD for external reference mode. The RESET pin must be driven low during power-up for at least 100 ns after supplies stabilize. SPI programming requires the chip select (SPI_CS) to be pulled high between transactions. Forgetting these details is a common cause of 'dead' ADC3423 boards; verify with the TI ADC342x datasheet's initialization sequence.
Compliance Information
RoHS and REACH compliant per TI product page. Not AEC-Q100 qualified (industrial grade only). Pin/lead-free finish and halogen-free per TI materials declaration.
