DSPIC33EP128GP502-I/MM - 16-bit DSC 70 MIPS 128KB Flash | Microchip
MPN: DSPIC33EP128GP502-I/MM ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $5.38 | $5.38 |
| 10 | $4.95 | $49.50 |
| 100 | $4.6 | $460.00 |
| 500 | $4.3 | $2,150.00 |
| 1,000 | $4.05 | $4,050.00 |
DSPIC33EP128GP502-I/MM Overview
A digital signal controller combines the control peripherals and ease of use of a microcontroller with the multiply-accumulate (MAC) computation power of a DSP. Within the embedded hierarchy, the dsPIC33EP family sits above general-purpose 8-bit MCUs and beside 16-bit microcontrollers, targeting real-time control loops such as digital power conversion, motor control, and signal processing where single-cycle MAC and DSP instruction support are essential.
Key features include the high-speed 70 MIPS dsPIC33E core with DSP engine, high-speed PWM modules suited to power conversion, on-chip op amps and advanced analog peripherals, ECAN (Controller Area Network), I2C, SPI, and UART communication interfaces, and up to 21 general-purpose I/O pins. The I-suffix temperature grade covers -40C to +125C for industrial environments.
Architecturally, the device uses a modified Harvard 16-bit core with a 2-stage pipeline, single-cycle MAC, hardware division support, and a Peripheral Trigger Generator (PTG) that automates peripheral-to-peripheral triggering to offload the CPU. Multiple pairs of PGECx/PGEDx pins support In-Circuit Serial Programming (ICSP) and debugging, and any pair may be used as long as PGECx and PGEDx are used together.
Typical applications include brushless DC and PMSM motor control, digital switched-mode power supplies and LED drivers, sensor fusion and signal conditioning nodes, and industrial automation with CAN networking.
When designing the PCB, place the VCAP capacitor on VDDCORE close to pin 24 and connect all VDD/VSS pairs; the exposed pad should be soldered to a ground pour for thermal and signal integrity. Budget flash and RAM headroom since 128 KB/16 KB is the mid-point of the GP502 family.
This page synthesizes distributor pricing, drop-in family alternatives, pinout, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for DSPIC33EP128GP502-I/MM — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33EP128GP502-I/MM (same form factor and footprint) — differing in Operating Temperature, Package, Communication Interfaces, RoHS Status, Lifecycle Status.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33EP256GP502-I/MM
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$3.79 / Unit
View Datasheet →DSPIC33EP64GP502-I/MM
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$2.2 / Unit
View Datasheet →DSPIC33EP32GP502-I/MM
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33EP128GP502-H/MM
✅ Drop-In✓ In Stock
Contact for price
View Datasheet →DSPIC33EP128GP502-E/MM
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33EP128GP502-I/MM Maximum Ratings & Electrical Characteristics
| Core | 16-bit dsPIC33E DSC |
| Maximum CPU Speed | 60 MHz (70 MIPS) |
| Flash Program Memory | 128 KB |
| RAM | 16 KB |
| Operating Voltage | 3.3 V (1.8 V minimum per datasheet range) |
| I/O Pins | 21 |
| Communication Interfaces | ECAN, I2C, SPI, UART |
| Special Peripherals | High-Speed PWM, Op Amps, Advanced Analog, PTG |
| Package | 28-pin QFN-S (6x6 mm) with exposed pad |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +125C (I grade) |
| Programming/Debug | ICSP via PGECx/PGEDx pairs |
| Product Status | In Production |
DSPIC33EP128GP502-I/MM Pin Configuration
| Pin 1 | MCLR — Master Clear (reset) input, programming voltage input for ICSP |
| Pin 2 | AN0/VREF+/CN2B/RA0 — Analog input 0 / ADC positive reference / change notification |
| Pin 3 | AN1/VREF-/CN3B/RA1 — Analog input 1 / ADC negative reference / change notification |
| Pin 4 | PGD1/AN2/C1IN-/RP0/RB0 — ICSP data 1, analog input 2, comparator input, remappable I/O |
| Pin 5 | PGC1/AN3/C1IN+/RP1/RB1 — ICSP clock 1, analog input 3, comparator input, remappable I/O |
| Pin 6 | AN4/CN6B/RP2/RB2 — Analog input 4, remappable peripheral I/O |
| Pin 7 | AN5/CN7B/RP3/RB3 — Analog input 5, remappable peripheral I/O |
| Pin 8 | VSS — Ground reference |
| Pin 9 | VDD — Positive supply (3.3 V nominal) |
| Pin 10 | PGD3/AN6/RP4/RB4 — ICSP data 3, analog input 6, remappable I/O |
| Pin 11 | PGC3/AN7/RP5/RB5 — ICSP clock 3, analog input 7, remappable I/O |
| Pin 12 | AN9/RP6/RB6 — Analog input 9, remappable peripheral I/O |
| Pin 13 | AN10/RP7/RB7 — Analog input 10, remappable peripheral I/O |
| Pin 14 | AN11/RP8/RB8 — Analog input 11, remappable peripheral I/O |
| Pin 15 | AN12/RP9/RB9 — Analog input 12, remappable peripheral I/O |
| Pin 16 | T5CK/RP10/RB10 — Timer5 clock input, remappable peripheral I/O |
| Pin 17 | T3CK/RP11/RB11 — Timer3 clock input, remappable peripheral I/O |
| Pin 18 | RP12/RB12 — Remappable peripheral I/O |
| Pin 19 | RP13/RB13 — Remappable peripheral I/O |
| Pin 20 | VSS — Ground reference |
| Pin 21 | VDD — Positive supply (3.3 V nominal) |
| Pin 22 | SOSCI/CN1/RP14/RB14 — Secondary oscillator input, remappable peripheral I/O |
| Pin 23 | SOSCO/T1CK/CN0/RP15/RB15 — Secondary oscillator output, Timer1 clock, remappable I/O |
| Pin 24 | VCAP/VDDCORE — Internal core regulator capacitor connection (external cap to VSS) |
| Pin 25 | PGD2/RP19 — ICSP data 2, remappable peripheral I/O (SDA1 capable) |
| Pin 26 | PGC2/RP18 — ICSP clock 2, remappable peripheral I/O (SCL1 capable) |
| Pin 27 | AVSS — Analog ground reference |
| Pin 28 | AVDD — Analog positive supply reference |
Typical Applications
DSPIC33EP128GP502-I/MM is suitable for 6 applications: Brushless DC / PMSM Motor Control, Digital Power Conversion (SMPS / PFC), CAN Networking Industrial Nodes, Sensor Signal Conditioning and Data Acquisition, LED Lighting and Electronic Ballasts, Portable and Battery-Powered Instruments.
Brushless DC / PMSM Motor Control
The DSPIC33EP128GP502-I/MM fits motor control because its high-speed PWM module generates complementary outputs with programmable dead time for three-phase inverters, while the 70 MIPS core with single-cycle MAC executes field-oriented control (FOC) inner loops well within PWM switching periods of 20-50 kHz. The Peripheral Trigger Generator can chain PWM events to ADC sampling of phase currents with hardware-level determinism, reducing CPU jitter. In a typical BLDC drive, the DSC reads current via its on-chip op amps and 12-bit ADC, runs Clarke/Park transforms and PI loops, and drives the gate stage directly. The 3.3 V supply and 21 I/O pins leave headroom for Hall/encoder inputs and fault protection.
Recommended
Digital Power Conversion (SMPS / PFC)
For digitally controlled switched-mode power supplies, the DSPIC33EP128GP502-I/MM provides the high-resolution high-speed PWM needed for buck, boost, and PFC stages, with ADC triggering synchronized to PWM for midpoint current sampling. The 70 MIPS core closes voltage and current loops at effective rates above 100 kHz, and the 128 KB Flash accommodates nonlinear compensation tables and soft-start state machines without external memory. ECAN allows the converter to report telemetry or accept setpoint commands in distributed power systems. Compared with analog controllers, the DSC enables adaptive compensation, firmware-configurable switching frequencies, and single-platform reuse across multiple power products, reducing qualification effort across a product family.
Recommended
CAN Networking Industrial Nodes
The integrated ECAN module makes the DSPIC33EP128GP502-I/MM a compact CAN 2.0B node for industrial automation, building control, and agricultural equipment. ECAN handles the CAN protocol in hardware with multiple receive buffers and filters, while the 70 MIPS core runs the application and signal conditioning concurrently. Sensor inputs are handled by the 12-bit ADC and on-chip op amps, and UART/SPI/I2C bridge local devices into the CAN bus. The -40C to +125C industrial temperature range and 28-pin QFN-S footprint suit sealed, space-constrained field modules. Firmware for bootloaders and protocol stacks fits comfortably in 128 KB Flash with room for future feature additions without hardware change.
Recommended
Sensor Signal Conditioning and Data Acquisition
The DSPIC33EP128GP502-I/MM integrates on-chip op amps and advanced analog peripherals, allowing it to amplify, filter, and digitize sensor signals - thermistors, strain gauges, pressure bridges, or current shunts - in a single chip. The 12-bit ADC supports simultaneous or sequential scans triggered by the PTG or a timer for deterministic sampling, and the DSP engine implements FIR/IIR filtering and FFT-based analysis at 70 MIPS. With 21 GPIOs, the same device drives displays, valves, or relays. This level of analog integration removes external instrumentation amplifiers in moderate-precision systems, cutting BOM cost and board area, while the QFN-S exposed pad provides a solid ground reference that benefits analog noise performance in compact designs.
Recommended
LED Lighting and Electronic Ballasts
Digitally controlled LED drivers benefit from the DSPIC33EP128GP502-I/MM's high-speed PWM and ADC loop: the controller regulates LED current via phase-shifted or frequency-modulated PWM, enforces dimming curves, and protects against open/short faults using fast ADC comparisons. The 70 MIPS core supports power-factor-correction plus constant-current control in a single chip for 50-200 W fixtures, while ECAN or UART enables DALI-like or DMX-adjacent control networks. 128 KB Flash stores multiple dimming profiles and calibration tables. The industrial temperature range suits enclosed luminaires with elevated ambient temperatures, and the compact 28-pin QFN-S fits driver boards where traditional through-hole controllers would not fit.
Recommended
Portable and Battery-Powered Instruments
Handheld measurement tools, gauges, and portable analyzers use the DSPIC33EP128GP502-I/MM where DSP-class math (RMS, FFT, curve fitting) must run on a battery budget. The 3.3 V operation, integrated peripherals, and small 6x6 mm QFN-S reduce overall solution size, while power-management features allow sleep/idle modes with periodic wakeups for long battery life. The 128 KB Flash stores UI assets, calibration data, and logging routines; 16 KB RAM buffers acquisition windows for on-device analysis. SPI/I2C connect displays, EEPROM, and sensors; UART provides service links. Compared with an MCU-plus-external-DSP split, the single-chip DSC architecture shortens firmware integration and shrinks the bill of materials significantly.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33EP128GP502-I/MM — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33EP256GP502-I/MM | DSPIC33EP64GP502-I/MM | DSPIC33EP32GP502-I/MM | DSPIC33EP128GP502-H/MM |
|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 28-pin QFN-S (6x6 mm) | 28-pin QFN-S - same | 28-pin QFN-S - same | 28-pin QFN-S - same | 28-pin QFN-S - same |
| Flash Memory | 128 KB | 256 KB | 64 KB | 32 KB | 128 KB |
| Max CPU Speed | 60 MHz (70 MIPS) | 60 MHz (70 MIPS) | 60 MHz (70 MIPS) | 60 MHz (70 MIPS) | 60 MHz (70 MIPS) |
| Temperature Grade | -40C to +125C (I) | -40C to +125C (I) | -40C to +125C (I) | -40C to +125C (I) | H grade (differs) |
| Communication Interfaces | ECAN, I2C, SPI, UART | ECAN, I2C, SPI, UART | ECAN, I2C, SPI, UART | ECAN, I2C, SPI, UART | ECAN, I2C, SPI, UART |
Key Differentiators
- Mid-family Flash size maximizes design margin (vs DSPIC33EP64GP502-I/MM)
- Cost-optimized alternative within the same footprint (vs DSPIC33EP256GP502-I/MM)
- Industrial temperature range for field equipment (vs DSPIC33EP128GP502-H/MM)
Design Notes
The QFN-S exposed pad must be soldered to a grounded copper pour - it is both the primary thermal path and the low-inductance ground return. Place the VCAP capacitor (pin 24, VDDCORE) within 1-2 mm of the pin with a direct via to ground; Microchip's datasheet specifies the required capacitance value for core regulation stability. Connect AVDD (pin 28) to VDD through an RC filter (e.g., 10 ohm + 1 uF) to isolate ADC noise, and tie AVSS (pin 27) directly to a quiet ground point near the exposed pad.
The dsPIC33EP128GP502 offers multiple PGECx/PGEDx pairs for ICSP. You may use any pair, but PGECx and PGEDx must be used together as a matched set - e.g., if PGEC2 (pin 26) carries ICSPCLK, ICSPDAT must go to PGED2 (pin 25). Mixing pairs from different sets is a common bring-up failure. Also ensure all VDD/VSS pairs (pins 8/9 and 20/21) are connected even if unused logic blocks suggest otherwise, and never float MCLR - use a 10 kohm pull-up for reliable reset behavior.
The device runs from a nominal 3.3 V rail; keep the supply within the datasheet operating range under all load transients, since the internal core regulator draws its current through VDD and the VCAP pin. Decouple each VDD pin with 0.1 uF ceramic plus a bulk 4.7-10 uF capacitor per power island. When PWM outputs drive MOSFET gate drivers, route high-current gate loops away from AVDD/ANx traces; the 70 MIPS core switching transient noise can couple into ADC readings and distort motor-control or power-conversion feedback loops.
Compliance Information
Compliance data was not explicitly present in the retrieved web data; consult the Microchip product page environmental datasheet for RoHS/REACH status.
