DSPIC33FJ128MC506A-H/MR - 16-bit 40 MIPS DSC | Microchip
MPN: DSPIC33FJ128MC506A-H/MR ✓ Active| Qty | Unit Price | Extended |
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| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
DSPIC33FJ128MC506A-H/MR Overview
A digital signal controller combines the computational throughput of a DSP with the peripheral integration and ease of use of a microcontroller. Within the power-management hierarchy, a DSC sits between a general-purpose MCU and a dedicated DSP: it executes a modified Harvard 16-bit architecture with DSP-grade multiply-accumulate instructions while retaining MCU-style peripherals such as UARTs, SPI, I2C, timers, and CAN, making it a single-chip solution for closed-loop power and motion systems.
Key features of the dsPIC33FJ128MC506A include hardware CAN 2.0B connectivity, a motor-control PWM module suited to brushless DC, single and 3-phase induction, and switched reluctance motors, plus a high-speed 12-bit ADC for current and voltage feedback loops. The A-version silicon is a revised die of the original dsPIC33FJ128MC506 with improved errata status. Multiple DMA channels offload the CPU during high-rate ADC sampling and serial transfers.
Architecturally, the device pairs a 16-bit pipelined core with a 24-bit instruction word, hardware looping, and bit-reversed addressing for FFT-type algorithms. PLL-based clocking allows an external 20 MHz input to be multiplied into the 40 MIPS operating range without external active components, simplifying crystal selection and EMC design.
Typical applications include brushless DC motor drives, single and 3-phase induction motor control, switched reluctance motors, uninterruptible power supplies, digital power converters, and general-purpose servo control. The rich analog and PWM peripheral set makes it well-suited to field-oriented control and sensorless schemes.
Design consideration: route the exposed pad of the QFN-64-EP to a solid ground plane, since it is the primary thermal and ground return path; decouple every VDD pin pair with low-ESR ceramics.
This page synthesizes distributor availability, drop-in family alternatives, pinout guidance, and practical design notes not consolidated in the manufacturer datasheet.
Drop-in alternatives for DSPIC33FJ128MC506A-H/MR — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33FJ128MC506A-H/MR (same form factor and footprint) — differing in Package, Core Architecture, Operating Temperature, SRAM, Timers.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33FJ128MC506A-I/MR
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$4.42 / Unit
View Datasheet →DSPIC33FJ128MC506A-E/MR
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$4.82 / Unit
View Datasheet →DSPIC33FJ256MC506A-H/MR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ64MC506A-H/MR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33FJ128MC506-H/MR
✅ Drop-In ⚠️ Specs Unverified📋 Reference alternative (not in catalog)
DSPIC33EP64MC206-E/MR
✅ Drop-In✓ In Stock
$3.2 / Unit
View Datasheet →DSPIC33FJ128MC506A-H/MR Maximum Ratings & Electrical Characteristics
| Core Architecture | 16-bit dsPIC33F DSC, modified Harvard |
| Maximum Execution Speed | 40 MIPS |
| Flash Program Memory | 128 KB |
| SRAM | 16 KB |
| Supply Voltage Range | 3 V to 3.6 V |
| Package | QFN-64-EP (9x9 mm), MR |
| CAN Module | ECAN, CAN 2.0B |
| Motor Control PWM | Yes (dedicated MCPWM module) |
| ADC | 12-bit, high-speed |
| DMA Channels | 8 |
| Timers | 11 |
| Serial Interfaces | UART, SPI, I2C |
| Input Oscillator | 20 MHz (PLL to 40 MIPS) |
| RoHS Status | RoHS3 Compliant |
| Mounting Type | Surface Mount |
| Part Status | Active |
DSPIC33FJ128MC506A-H/MR Pin Configuration
| Pin 1 | MCLR — Master clear reset input |
| Pin 2 | VSS — Ground reference |
| Pin 3 | VDD — Power supply (3.0-3.6 V) |
| Pin 4 | ENVREG/VCAP — Regulator enable / regulator output capacitor |
| Pin 5 | RB0/AN0 — Port B bit 0 / analog input 0 |
| Pin 6 | RB1/AN1 — Port B bit 1 / analog input 1 |
| Pin 7 | RB2/AN2 — Port B bit 2 / analog input 2 |
| Pin 8 | RB3/AN3 — Port B bit 3 / analog input 3 |
| Pin 9 | VDD — Power supply |
| Pin 10 | VSS — Ground reference |
| Pin 11 | RB4/AN4 — Port B bit 4 / analog input 4 |
| Pin 12 | RB5/AN5 — Port B bit 5 / analog input 5 |
| Pin 13 | RB6/PGC — Port B bit 6 / ICSP clock |
| Pin 14 | RB7/PGD — Port B bit 7 / ICSP data |
| Pin 15 | RB8 — Port B bit 8 |
| Pin 16 | RB9 — Port B bit 9 |
| Pin 17 | VDD — Power supply |
| Pin 18 | VSS — Ground reference |
| Pin 19 | RB10 — Port B bit 10 |
| Pin 20 | RB11 — Port B bit 11 |
| Pin 21 | RB12 — Port B bit 12 |
| Pin 22 | RB13 — Port B bit 13 |
| Pin 23 | RB14 — Port B bit 14 |
| Pin 24 | RB15 — Port B bit 15 |
| Pin 25 | VDD — Power supply |
| Pin 26 | VSS — Ground reference |
| Pin 27 | RD0 — Port D bit 0 / PWM output |
| Pin 28 | RD1 — Port D bit 1 / PWM output |
| Pin 29 | RD2 — Port D bit 2 / PWM output |
| Pin 30 | RD3 — Port D bit 3 / PWM output |
| Pin 31 | RD4 — Port D bit 4 / PWM output |
| Pin 32 | RD5 — Port D bit 5 / PWM output |
| Pin 33 | RD6 — Port D bit 6 / PWM output |
| Pin 34 | RD7 — Port D bit 7 / PWM output |
| Pin 35 | VDD — Power supply |
| Pin 36 | VSS — Ground reference |
| Pin 37 | RD8 — Port D bit 8 |
| Pin 38 | RD9 — Port D bit 9 |
| Pin 39 | RD10 — Port D bit 10 |
| Pin 40 | RD11 — Port D bit 11 |
| Pin 41 | RD12 — Port D bit 12 |
| Pin 42 | RD13 — Port D bit 13 |
| Pin 43 | RD14 — Port D bit 14 |
| Pin 44 | RD15 — Port D bit 15 |
| Pin 45 | RF2/U1RX — Port F bit 2 / UART1 receive |
| Pin 46 | RF3/U1TX — Port F bit 3 / UART1 transmit |
| Pin 47 | RF6 — Port F bit 6 |
| Pin 48 | RF7 — Port F bit 7 |
| Pin 49 | VDD — Power supply |
| Pin 50 | VSS — Ground reference |
| Pin 51 | RF8 — Port F bit 8 |
| Pin 52 | RF12 — Port F bit 12 |
| Pin 53 | RF13 — Port F bit 13 |
| Pin 54 | RC1 — Port C bit 1 |
| Pin 55 | RC2 — Port C bit 2 |
| Pin 56 | RC3 — Port C bit 3 |
| Pin 57 | RC4 — Port C bit 4 |
| Pin 58 | AVDD — Analog power supply |
| Pin 59 | AVSS — Analog ground |
| Pin 60 | RC12/OSC1 — Port C bit 12 / oscillator input |
| Pin 61 | RC15/OSC2 — Port C bit 15 / oscillator output |
| Pin 62 | VDD — Power supply |
| Pin 63 | VSS — Ground reference |
| Pin 64 | RF4 — Port F bit 4 |
Typical Applications
DSPIC33FJ128MC506A-H/MR is suitable for 6 applications: Brushless DC Motor Control, 3-Phase Induction Motor Drives, Digital Power and UPS Systems, Automotive Auxiliary Motor Control, Switched Reluctance Motor Drives, Industrial Robotics and Servo Drives.
Brushless DC Motor Control
The dsPIC33FJ128MC506A family is explicitly optimized by Microchip for brushless DC (BLDC) motor applications. Its dedicated motor-control PWM module generates complementary, dead-time-controlled six-step or sinusoidal drive signals, while the 12-bit high-speed ADC samples phase currents fast enough for cycle-by-cycle current limiting. The 40 MIPS DSP core executes commutation tables or sensorless observers with headroom for field-oriented control. In a typical 3.3 V-signal drive stage, PWM outputs feed a gate-driver IC that levels-shifts to the power MOSFET bridge, with the controller supervising bus voltage and fault shutdown via its DMA-assisted ADC scanning.
Recommended
3-Phase Induction Motor Drives
Single and 3-phase induction motor control is a headline application for the dsPIC33FJ128MC506A per the Microchip product page. The 40 MIPS core runs V/f control or rotor-flux-oriented algorithms, while the motor-control PWM module produces the three-phase inverter gating with programmable dead time. The 12-bit ADC captures DC-bus current via shunt or current-sensor feedback, and the ECAN module links the drive to factory networks. The 128 KB Flash accommodates parameter tables, ramp profiles, and communication stacks, and the H temperature grade suits drives mounted near hot enclosures.
Recommended
Digital Power and UPS Systems
In uninterruptible power supplies, solar inverters, and PFC stages, the DSPIC33FJ128MC506A closes high-bandwidth control loops with its 12-bit ADC triggered by the PWM module for cycle-aligned sampling. The 40 MIPS throughput supports multi-loop voltage/current control executed every switching cycle, and 8 DMA channels move ADC results without CPU intervention, preserving jitter-free timing. The GS-series digital-power relatives (DSPIC33FJ06GS202) share this design pattern. The controller's CAN and UART ports handle supervisory communication with battery management and display boards.
Recommended
Automotive Auxiliary Motor Control
The CAN 2.0B ECAN module makes the dsPIC33FJ128MC506A a fit for auxiliary automotive motor loads such as pumps, fans, actuators, and throttle-by-wire subsystems that communicate on a CAN bus. The H extended temperature variant tolerates underhood-adjacent ambient conditions better than commercial parts. Its 12-bit ADC supports resolver-free current sensing, and the motor-control PWM drives integrated bridge drivers. Note: verify the exact H-grade qualification level against the datasheet before use in safety-critical automotive positions, since AEC-Q100 status must be confirmed from the ordering table.
Recommended
Switched Reluctance Motor Drives
Microchip lists switched reluctance (SR) motors among the target machines for the dsPIC33FJ128MC506A family. SR drives demand asymmetric PWM phase excitation with precise rotor-position tracking, which the motor-control PWM module plus quadrature/position inputs and the fast 12-bit ADC handle directly. The 40 MIPS core executes torque-sharing tables and phase-current commutation in real time, while 128 KB Flash stores magnetic characteristic maps for efficiency optimization. The ECAN port enables drivetrain-level coordination in traction and industrial pump systems using SR machines.
Recommended
Industrial Robotics and Servo Drives
For robotic joints and servo axes, the DSPIC33FJ128MC506A provides the DSP math (multiply-accumulate, hardware looping) needed for cascaded position/velocity/current loops at multi-kilohertz rates, executing field-oriented control of PMSM motors with encoder or sensorless feedback into its 12-bit ADC. Four serial ports support drive buses, encoders with protocol conversion, and host communication, while ECAN integrates the axis into machine-level networks. The 3.0-3.6 V core interfaces cleanly with 3.3 V gate drivers and isolation devices on a single-rail servo board.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33FJ128MC506A-H/MR — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33FJ128MC506A-I/MR | DSPIC33FJ256MC506A-H/MR | DSPIC33FJ64MC506A-H/MR | DSPIC33EP64MC206-E/MR |
|---|---|---|---|---|---|
| Package | QFN-64-EP (9x9 mm), MR | QFN-64-EP (9x9 mm) - same | QFN-64-EP (9x9 mm) - same | QFN-64-EP (9x9 mm) - same | QFN-64 - same footprint class |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Flash Memory | 128 KB | 128 KB | 256 KB | 64 KB | 64 KB |
| Core Performance | 40 MIPS, 16-bit | 40 MIPS, 16-bit | 40 MIPS, 16-bit | 40 MIPS, 16-bit | up to 70 MIPS, 16-bit EP core |
| CAN Module | ECAN, CAN 2.0B | ECAN, CAN 2.0B | ECAN, CAN 2.0B | ECAN, CAN 2.0B | ECAN (verify pin mux) |
| Silicon Revision | A revision (improved errata) | A revision | A revision | A revision | newer EP core generation |
| Software Compatibility | dsPIC33FJ toolchain (MPLAB X, XC16) | 100% identical | 100% identical | 100% identical | same XC16 toolchain, register-level port needed |
Key Differentiators
- Extended H temperature grade with full motor-control peripheral set (vs DSPIC33FJ128MC506A-I/MR)
- 128 KB Flash balance of cost and headroom (vs DSPIC33FJ64MC506A-H/MR)
- A-revision silicon errata status (vs DSPIC33FJ128MC506-H/MR)
- Same toolchain, lower clock than EP generation (vs DSPIC33EP64MC206-E/MR)
Design Notes
The exposed pad of the QFN-64-EP is the main ground return and thermal path. Define a dedicated ground keep-out under the device with a 5x5 or denser via array stitched to the internal ground plane, and ensure the stencil prints about 70-80% pad coverage with segmented apertures to prevent voiding during reflow. All VDD/AVDD pins need a 0.1 uF ceramic within 2 mm, plus one 4.7-10 uF bulk capacitor near the supply entry. Keep the VCAP/ENVREG regulator pin capacitor per datasheet value for stable internal core regulation.
Motor-control PWM edges switching amperes on the inverter will couple into the 12-bit ADC front end if routing is careless. Route analog sense lines (phase current shunt amplifiers, bus voltage dividers) on a separate analog island around AVDD/AVSS, and keep them physically away from PWM and CAN traces. Use PWM-triggered ADC sampling so current sampling occurs away from switching transitions; the DMA channels can move results with zero CPU jitter. Add small RC filters (about 100 ohm / 1 nF, bandwidth permitting) on analog inputs.
Three common mistakes: (1) leaving the ENVREG/VCAP pin misconfigured - if the internal regulator is enabled, the correct capacitor must be present or the device will not start; (2) assuming 5 V tolerance - the 3.0-3.6 V rails are not 5 V tolerant, so level-shift any 5 V signals; (3) using non-A dsPIC33FJ128MC506 errata assumptions - this is the A revision, so re-check the Microchip errata document against your workaround list before reusing older firmware workarounds. Also configure MCLR with a pull-up and series resistor for robust ICSP programming.
Compliance Information
RoHS3 compliant per ics-embedded and JLCPCB distributor listings. REACH, halogen-free, and conflict-minerals status not stated in retrieved data.
