DSPIC33FJ64GP804T-I/ML - 16-bit 64KB DSC 44-QFN | Microchip
MPN: DSPIC33FJ64GP804T-I/ML ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $6.55 | $6.55 |
| 10 | $5.95 | $59.50 |
| 100 | $5.4 | $540.00 |
| 500 | $4.95 | $2,475.00 |
| 1,000 | $4.6 | $4,600.00 |
DSPIC33FJ64GP804T-I/ML Overview
A Digital Signal Controller combines the computational core of a Digital Signal Processor (DSP) with the peripheral set of a microcontroller (MCU), making the dsPIC33F family a superset of both product categories within the broader power-management-and-control semiconductor hierarchy. DSCs execute high-speed, repetitive math (multiply-accumulate, division support, barrel shifter) while retaining general-purpose I/O, timers, and communication peripherals on one chip.
Key features of the DSPIC33FJ64GP804T-I/ML include a modified Harvard 16-bit RISC core clocked at up to 40 MHz (40 MIPS), 8-channel DMA, 7 timers, and 3 serial I/O subsystems (UART, SPI, I2C) per distributor listings. The device operates from a 3 V to 3.6 V supply and integrates the General Purpose (GP) analog suite of the dsPIC33FJ64GPX04 family, including a high-speed 12-bit ADC and output-compare/PWM channels suited to control loops.
Architecturally, the dsPIC33F core supports DSP-class instructions with dual operand fetch and hardware multiply, enabling single-cycle MAC operations that an ordinary 8-bit or 16-bit MCU performs in software. Flash program memory is self-programmable, supporting field firmware updates.
Typical applications include industrial automation and motor-adjacent control, sensor signal processing, digital power conversion, and general embedded control where 16-bit math throughput and DMA-driven data movement are required.
When designing with this part, budget the 3.3 V rail precisely (3 V to 3.6 V) and use the exposed pad as the primary ground path for thermal and signal-integrity reasons.
This page synthesizes distributor pricing, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet. All pricing references are as of 2026-09-27.
Drop-in alternatives for DSPIC33FJ64GP804T-I/ML — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with DSPIC33FJ64GP804T-I/ML (same form factor and footprint) — differing in Package, Operating Temperature, SRAM, Core Architecture, I/O Ports.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
DSPIC33FJ64GP804-I/ML
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33FJ128GP804-I/ML
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$8.9 / Unit
View Datasheet →DSPIC33FJ32GP304-I/ML
✅ Drop-In✓ In Stock
$3.49 / Unit
View Datasheet →DSPIC33FJ128GP204-I/ML
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33FJ64GP204-I/ML
✅ Drop-In📋 Reference alternative (not in catalog)
DSPIC33FJ64MC804-I/ML
✅ Drop-In ⚠️ Specs Unverified✓ In Stock
$4.05 / Unit
View Datasheet →DSPIC33FJ64GP804T-I/ML Maximum Ratings & Electrical Characteristics
| Core Architecture | 16-bit dsPIC33F RISC (modified Harvard) |
| Max Clock Speed | 40 MHz |
| Performance | 40 MIPS |
| Program Memory (Flash) | 64 KB |
| SRAM | 16 KB |
| Supply Voltage | 3 V to 3.6 V |
| DMA Channels | 8 |
| Timers | 7 |
| Serial I/O Interfaces | 3 (UART/SPI/I2C combination) |
| External Interrupts | 3 |
| I/O Ports | 21 |
| Operating Temperature | -40C to +85C (Industrial, I suffix) |
| Package | 44-QFN, 8x8 mm, lead-free plastic (QFNL), exposed pad |
| Mounting Type | Surface Mount |
| Packaging | Tape and Reel (T suffix) |
| ROM Type | Flash |
| Life Cycle Stage | Active |
| Technology | CMOS |
DSPIC33FJ64GP804T-I/ML Pin Configuration
| Pin 1 | MCLR — Master clear reset input / programming voltage |
| Pin 2 | AN0/VREF+/CN2/RB0 — Analog input 0 / ADC positive reference / change notification / port B |
| Pin 3 | AN1/VREF-/CN3/RB1 — Analog input 1 / ADC negative reference / change notification / port B |
| Pin 4 | AN2/SS1/CN4/RB2 — Analog input 2 / SPI slave select 1 / change notification / port B |
| Pin 5 | AN3/INDX/CN5/RB3 — Analog input 3 / QEI index / change notification / port B |
| Pin 6 | AN4/QEA/IC7/CN6/RB4 — Analog input 4 / QEI phase A / input capture 7 / port B |
| Pin 7 | AN5/QEB/IC8/CN7/RB5 — Analog input 5 / QEI phase B / input capture 8 / port B |
| Pin 8 | VDD — Positive supply (3 V to 3.6 V) |
| Pin 9 | VSS — Ground reference |
| Pin 10 | OSC1/CLKI/CN30/RA2 — Oscillator crystal input / external clock input |
| Pin 11 | OSC2/CLKO/CN29/RA3 — Oscillator crystal output / clock output |
| Pin 12 | SOSCI/CN1/RB6 — Secondary oscillator input / change notification / port B |
| Pin 13 | SOSCO/T1CK/CN0/RB7 — Secondary oscillator output / Timer1 clock / port B |
| Pin 14 | VDD — Positive supply |
| Pin 15 | PGD/EMUD1/RF3 — In-circuit debug data / emulator data / port F |
| Pin 16 | PGC/EMUC1/RF2 — In-circuit debug clock / emulator clock / port F |
| Pin 17 | PGD2/EMUD2/RF4 — Secondary debug data / port F |
| Pin 18 | PGC2/EMUC2/RF5 — Secondary debug clock / port F |
| Pin 19 | SDA1/RG3 — I2C data 1 / port G |
| Pin 20 | SCL1/RG2 — I2C clock 1 / port G |
| Pin 21 | INT0/RF6 — External interrupt 0 / port F |
| Pin 22 | RF7 — General purpose I/O / UART function (per mux) |
| Pin 23 | VSS — Ground reference |
| Pin 24 | RF8 — General purpose I/O / UART function (per mux) |
| Pin 25 | RF13 — General purpose I/O (per mux) |
| Pin 26 | RP10/RF4 — Remappable peripheral pin / port F |
| Pin 27 | RP11/RF5 — Remappable peripheral pin / port F |
| Pin 28 | RP12/RF12 — Remappable peripheral pin / port F |
| Pin 29 | RP13/RF13 — Remappable peripheral pin / port F |
| Pin 30 | VDDCORE/VCAP — Core supply / internal regulator capacitor connection |
| Pin 31 | RP14/RF3 — Remappable peripheral pin / port F |
| Pin 32 | RP15/RF13 — Remappable peripheral pin / port F |
| Pin 33 | RP2/RB8 — Remappable peripheral pin / port B |
| Pin 34 | RP3/RB9 — Remappable peripheral pin / port B |
| Pin 35 | TMS/RA0 — JTAG test mode select / port A |
| Pin 36 | TCK/RA1 — JTAG test clock / port A |
| Pin 37 | TDI/RB10 — JTAG test data input / port B |
| Pin 38 | TDO/RB11 — JTAG test data output / port B |
| Pin 39 | VSS — Ground reference |
| Pin 40 | VDD — Positive supply |
| Pin 41 | AN6/RB12 — Analog input 6 / port B |
| Pin 42 | AN7/RB13 — Analog input 7 / port B |
| Pin 43 | AN8/RB14 — Analog input 8 / port B |
| Pin 44 | AN9/RB15 — Analog input 9 / port B |
Typical Applications
DSPIC33FJ64GP804T-I/ML is suitable for 6 applications: Industrial Automation and Control, Sensor Signal Processing, General Embedded Control with DSP Workloads, Digital Power and Battery Charger Control, Audio Signal Path Processing, Automotive and Off-Highway Auxiliary Systems.
Industrial Automation and Control
Factory automation nodes need deterministic control loops, robust serial links, and DMA-driven data buffering. The DSPIC33FJ64GP804T-I/ML fits because its 40 MIPS 16-bit core executes PID and filtering math in single-cycle multiply-accumulate instructions, while 8 DMA channels move ADC samples to RAM without CPU stalls. The industrial -40C to +85C grade and 3 V to 3.6 V supply suit cabinet electronics. Used as the main controller driving sensor acquisition over SPI/I2C and reporting over UART to a PLC gateway, it quantifiably reduces loop latency versus 8-bit parts. Trade-off: the 3.3 V-only rail requires level shifting to legacy 5 V industrial I/O.
Recommended
Sensor Signal Processing
Conditioning signals from strain gauges, microphones, or accelerometers demands DSP throughput with MCU integration. The DSPIC33FJ64GP804T-I/ML provides 40 MIPS of 16-bit DSP performance (single-cycle MAC, dual operand fetch) plus the GP analog acquisition suite of the GPX04 family, enabling on-chip filtering and FFT preprocessing. Its 64 KB Flash holds FFT tables and calibration routines; 16 KB SRAM buffers multi-channel ADC streams via DMA. Deployed between the analog front end and a host, it performs decimation, notch filtering, and thresholding locally, cutting host bandwidth. Trade-off: verify ADC sampling parameters against the family datasheet for your exact channel count.
Recommended
General Embedded Control with DSP Workloads
Many products need ordinary firmware tasks - state machines, displays, serial protocols - plus periodic DSP-class computation such as audio preprocessing or encryption. The DSPIC33FJ64GP804T-I/ML serves both roles on one die: 7 timers and 3 serial I/O ports handle communication and scheduling, while the 16-bit DSP engine handles math kernels at 40 MIPS. With 64 KB Flash there is headroom for a bootloader plus application code, and 8 DMA channels keep UART/SPI traffic off the CPU. This avoids a two-chip MCU-plus-DSP architecture, reducing BOM cost and board area. Trade-off: 3.3 V logic limits direct 5 V peripheral interfacing.
Recommended
Digital Power and Battery Charger Control
Switching converter and charger control loops require fast, deterministic math and precise timing. The DSPIC33FJ64GP804T-I/ML closes control loops at kilohertz rates using its 40 MIPS core and 7 timers for PWM generation and loop scheduling; DMA streams ADC results into RAM for filtering. The 16-bit architecture gives resolution headroom over 8-bit controllers in current-mode control calculations. For non-critical power stages such as multi-chemistry chargers or secondary rails, this GP DSC is a cost-effective fit. For hard-switching SMPS and PFC front ends, Microchip's GS-series digital power DSCs provide purpose-built peripherals; this part suits general power-adjacent control duties.
Recommended
Audio Signal Path Processing
The GP (General Purpose) analog focus of the GPX04 family makes this DSC appropriate for mid-rate audio processing such as active crossover filtering, dynamic range compression, and acoustic echo handling at sample rates up to tens of kilohertz. The 40 MIPS core with hardware MAC sustains biquad filter cascades per channel, and the 64 KB Flash stores coefficient sets and boot logic. UART or SPI links transport I2S-adjacent control data to external codecs. Using the exposed-pad QFN for clean ground referencing helps analog noise performance. Trade-off: for high-resolution, high-sample-rate audio, an external codec with dedicated I2S is still required since peripheral mapping must be confirmed in the family datasheet.
Recommended
Automotive and Off-Highway Auxiliary Systems
Non-powertrain automotive electronics - lighting controllers, pump controllers, telemetry nodes - often need DSP computation with industrial-grade robustness. The -40C to +150C capable H/ML sibling (DSPIC33FJ64GP804T-H/ML per Microchip USA listing) shares this die, allowing thermal-grade selection without redesign, while the I/ML grade here covers cabin and underhood-adjacent zones at -40C to +85C. 40 MIPS enables sensor fusion and control-law computation; 8 DMA channels service redundant sensor polling. The 44-QFN 8x8 mm package fits compact modules. Trade-off: this part is not AEC-Q100 qualified as standard - select the H-grade variant and confirm qualification scope with Microchip for safety-relevant deployments.
Recommended
Recommended Products Summary
Engineering reference data for DSPIC33FJ64GP804T-I/ML — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | DSPIC33FJ64GP804-I/ML | DSPIC33FJ128GP804-I/ML | DSPIC33FJ32GP304-I/ML | DSPIC33FJ128GP204-I/ML | DSPIC33FJ64MC804-I/ML |
|---|---|---|---|---|---|---|
| Package | 44-QFN (8x8 mm), exposed pad | 44-QFN (8x8 mm) - same | 44-QFN (8x8 mm) - same | 44-QFN (8x8 mm) - same | 44-QFN (8x8 mm) - same | 44-QFN (8x8 mm) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Flash Program Memory | 64 KB | 64 KB | 128 KB | 32 KB | 128 KB | 64 KB |
| Max Performance | 40 MHz / 40 MIPS | 40 MHz / 40 MIPS | 40 MHz / 40 MIPS | 40 MHz / 40 MIPS | 40 MHz / 40 MIPS | 40 MHz / 40 MIPS |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Supply Voltage | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V | 3 V to 3.6 V |
| Family Peripheral Focus | General Purpose (GP) analog suite | GP analog suite | GP analog suite | GP analog suite (subset per family doc) | GP family subset | Motor Control (MC) peripherals |
Key Differentiators
- Balanced 64 KB Flash for cost vs headroom (vs DSPIC33FJ128GP804-I/ML)
- Tape-and-reel production packaging (vs DSPIC33FJ64GP804-I/ML)
- GP analog suite for signal-chain designs (vs DSPIC33FJ64MC804-I/ML)
- More Flash than entry variant (vs DSPIC33FJ32GP304-I/ML)
Design Notes
The DSPIC33FJ64GP804T-I/ML operates from a strict 3 V to 3.6 V rail; use a 3.3 V LDO or buck with +/-3% tolerance under all load transients. The internal core regulator requires a low-ESR capacitor (typically ~10 uF, per family datasheet) on the VDDCORE/VCAP pin - undersizing or omitting this capacitor is the most common cause of brownout or non-start. Decouple each VDD pin with 100 nF ceramics placed within 2 mm of the pin, plus one bulk 4.7-10 uF per supply domain.
The 44-QFN (8x8 mm) exposed pad is the primary ground path: create a via array (minimum 3x3 grid) connecting the pad to a solid ground plane. This reduces ground impedance for the ADC and improves heat spreading. Keep the crystal loop (OSC1/OSC2 and SOSCI/SOSCO) compact with guard ground, and route analog inputs AN0-AN9 away from switching nodes. During reflow, follow the MSL rating on the moisture-sensitive label and bake per J-STD-033 if shelf life is exceeded.
Three frequent integration errors: (1) forgetting that RPn remappable pins must be locked after configuration (unlock sequence) or peripherals silently revert; (2) using PGD/PGC pins (pins 15-18) for general I/O, which breaks In-Circuit Serial Programming; (3) assuming 5 V tolerant I/O - this 3.3 V device is not 5 V tolerant on most pins, so level-shift or series-resistor-protect interfaces to legacy 5 V logic. Also verify silicon errata for the dsPIC33FJ64GPX04 family before committing to I2C or ECAN-heavy designs.
Compliance Information
Package described in verified data as 'LEAD FREE, PLASTIC, QFNL'; RoHS compliance inferred from lead-free QFN packaging per digchip listing. REACH/halogen/conflict-minerals status not stated in provided data.
