EP1AGX35DF780C6N - Arria GX FPGA, 33.5K LEs, 3.125 Gbps | Altera
MPN: EP1AGX35DF780C6N β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $268.5 | $2,685.00 |
| 100 | $245 | $24,500.00 |
| 500 | $222 | $111,000.00 |
| 1,000 | $199.5 | $199,500.00 |
Drop-in alternatives for EP1AGX35DF780C6N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EP1AGX35CF780C6N
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EP1AGX35CF780I6N
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EP1AGX50CF780I6N
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View Datasheet βEP1AGX35DF780C6N Maximum Ratings & Electrical Characteristics
| Family | Arria GX |
| Logic Elements (LEs) | 33,520 |
| Adaptive Logic Modules (ALMs) | 16,725 |
| Embedded Memory | 1,348,416 bits (1.35 Mbit) |
| Logic Array Blocks (LABs) | 1,676 |
| Maximum User I/O | 341 |
| Transceivers | Up to 8 channels |
| Transceiver Data Rate | 600 Mbps to 3.125 Gbps |
| PLLs | 4 total (2 fast + 2 enhanced) |
| Core Voltage | 1.2 V |
| Process Technology | 90 nm |
| Speed Grade | C6 (standard performance) |
| Package | 780-ball FC-FBGA (DF) |
| Package Dimensions | 29 x 29 mm, 1.0 mm pitch |
| Operating Temperature | Commercial 0C to 85C (TJ) |
| Mounting Type | Surface Mount (BGA) |
| Lead Free | Yes |
| Configuration Modes | PS, FPP, JTAG, AES encryption |
EP1AGX35DF780C6N 29 x 29 mm, 1.0 mm pitch Pin Configuration Guide
Complete pinout information for EP1AGX35DF780C6N (29 x 29 mm, 1.0 mm pitch package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1AGX35DF780C6N.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1AGX35DF780C6N is suitable for 6 applications: PCI Express Gen1 Endpoint Cards, Gigabit Ethernet / XAUI Line Cards, Serial RapidIO Wireless Baseband Bridges, Broadcast Video Routers and Switchers, High-Speed Serial Backplane Bridging, Industrial Test and Measurement Equipment.
PCI Express Gen1 Endpoint Cards
The EP1AGX35DF780C6N's 8 hardened 3.125 Gbps transceivers natively support PCI Express Gen1 (2.5 Gbps) endpoints with the integrated hard IP core for x1/x4/x8 link widths. The 1,348,416 bits of embedded memory comfortably buffer DMA descriptors and payload FIFOs, while 33,520 LEs host the PCIe application layer including MSI-X, completion timeout, and link-state logic. Designers benefit from the FC-FBGA package's 1.0 mm pitch which is compatible with standard 4-layer PCBs and inexpensive microvia stackup. Compared with a soft-IP PCIe solution on a Stratix-class device, this part reduces LE consumption by 40-60% and simplifies timing closure on multi-gigabit interfaces.
Recommended
Gigabit Ethernet / XAUI Line Cards
The Arria GX transceiver hard IP supports 1000BASE-X SGMII and 10 Gigabit Ethernet XAUI (4 x 3.125 Gbps lanes) directly, eliminating the need for external PHY devices. The EP1AGX35DF780C6N's 8 transceiver channels allow a single chip to implement a quad-port Gigabit Ethernet switch or a single XAUI port plus housekeeping interfaces. The 4 PLLs (2 fast + 2 enhanced) generate the multiple reference clocks required for XAUI lane alignment. With 341 user I/O the device easily drives external MAC/PHY glue logic, packet classification engines, and management plane interfaces on the same die.
Recommended
Serial RapidIO Wireless Baseband Bridges
Serial RapidIO (SRIO) at 1.25, 2.5, and 3.125 Gbps per lane is widely deployed in wireless base stations to interconnect DSP clusters with FPGAs acting as bridges between SRIO links and backplane fabrics. The EP1AGX35DF780C6N's 8 transceivers deliver up to 25 Gbps aggregate bandwidth, enough for 8x SRIO x1 lanes or 2x x4 links to dual DSP cards. The TriMatrix memory supports 1,348,416 bits of buffering for ingress packets, and the fast PLLs provide the low-jitter reference clocks demanded by SRIO link training. Commercial temperature grade suits indoor base-station deployments.
Recommended
Broadcast Video Routers and Switchers
Broadcast studios need to switch uncompressed SDI video streams at 270 Mbps, 1.485 Gbps (HD-SDI), or 2.97 Gbps (3G-SDI) - all of which fit within the EP1AGX35DF780C6N's 3.125 Gbps transceiver envelope. Each of the 8 channels can clock out an SDI stream independently while embedded memory holds audio and ANC data buffers. The 33,520 LEs host audio de-embedding, frame synchronizers, and routing matrix logic, while 341 user I/O pins drive downstream HDMI / DisplayPort encoders or GPIO to studio control panels. The 780-FBGA package dissipates heat through the package backside, suitable for rack-mounted cooled chassis.
Recommended
High-Speed Serial Backplane Bridging
Industrial imaging and test systems often backhaul multiple sensor lanes over a high-speed serial backplane operating at 1.5-3.125 Gbps. The EP1AGX35DF780C6N aggregates up to 8 sensor channels and re-drives them across a backplane or fiber link, while 33,520 LEs implement sensor pre-processing, timestamp insertion, and CRC generation. The 1.0 mm-pitch FC-FBGA package enables standard 4-layer PCB stackups with microvia fanout, keeping backplane card costs low. Embedded TriMatrix memory stores line buffers and lookup tables for sensor calibration.
Recommended
Industrial Test and Measurement Equipment
Automated Test Equipment (ATE) for RF, mixed-signal, and high-speed digital devices needs parallel multi-gigabit serial interfaces and real-time DSP for protocol-aware measurements. The EP1AGX35DF780C6N provides 8 transceivers up to 3.125 Gbps for connecting to DUTs via SATA, PCIe, XAUI, or proprietary links, while 33,520 LEs host pattern generators, error counters, and protocol analyzers. The 1,348,416 bits of embedded memory act as waveform / pattern buffers, and the 341 user I/O drive external DAC/ADC analog front-ends. Commercial temperature grade suits benchtop instrumentation in climate-controlled labs.
Recommended
Recommended Products Summary
Engineering reference data for EP1AGX35DF780C6N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1AGX35CF780C6N | EP1AGX35CF780I6N | EP1AGX50CF780C6N | EP1AGX50CF780I6N | EP1AGX20CF780C6N | EP1AGX35DF780C6 |
|---|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 780-ball FC-FBGA (DF) | 780-ball FC-FBGA (CF) - same footprint | 780-ball FC-FBGA (CF) - same footprint | 780-ball FC-FBGA (CF) - same footprint | 780-ball FC-FBGA (CF) - same footprint | 780-ball FC-FBGA (CF) - same footprint | 780-ball FC-FBGA (DF) - same footprint |
| Logic Elements | 33,520 | 33,520 (same) | 33,520 (same) | 50,160 (+49.7%) | 50,160 (+49.7%) | 20,140 (-39.9%) | 33,520 (same) |
| Embedded Memory (bits) | 1,348,416 | 1,348,416 (same) | 1,348,416 (same) | 2,475,072 (+83.6%) | 2,475,072 (+83.6%) | 1,230,720 (-8.7%) | 1,348,416 (same) |
| User I/O | 341 | 341 (same) | 341 (same) | 341 (same) | 341 (same) | 341 (same) | 341 (same) |
| Transceivers | 8 @ up to 3.125 Gbps | 8 @ up to 3.125 Gbps (same) | 8 @ up to 3.125 Gbps (same) | 8 @ up to 3.125 Gbps (same) | 8 @ up to 3.125 Gbps (same) | 8 @ up to 3.125 Gbps (same) | 8 @ up to 3.125 Gbps (same) |
| Speed Grade | C6 | C6 (same) | I6 (faster corner) | C6 (same) | I6 (faster corner) | C6 (same) | C6 (same) |
| Operating Temperature | Commercial 0C to 85C | Industrial -40C to 100C | Industrial -40C to 100C | Industrial -40C to 100C | Industrial -40C to 100C | Industrial -40C to 100C | Commercial 0C to 85C |
Key Differentiators
- Pin-compatible density and temperature options within Arria GX family (vs EP1AGX35CF780C6N vs EP1AGX20CF780C6N)
- Highest LEs at the commercial C6 speed grade in 780-FBGA (vs EP1AGX35DF780C6N vs EP1AGX35CF780I6N)
- Pure commercial temperature grade with no 'N' trailing designator (vs EP1AGX35DF780C6 vs EP1AGX35DF780C6N)
Design Notes
Estimated: BGA breakout at 1.0 mm ball pitch on the EP1AGX35DF780C6N requires at least 4 PCB layers with 0.2 mm via-pad diameter microvias-in-pad. The 780-ball array needs approximately 12 mm of perimeter space for signal fanout on outer layers before via stitching becomes possible. Use 1 oz copper on outer layers and 0.5 oz on inner layers for controlled-impedance traces around the BGA. Add a continuous GND pour under the package die-up area to provide a low-impedance reference plane for the transceivers' return currents.
According to the Arria GX device handbook, transceiver reference clock jitter must be below 1 ps RMS (12 kHz to 20 MHz) for 3.125 Gbps operation. Use a dedicated low-jitter clock generator with a clean power supply; isolate the clock generator from the FPGA core VCC using a ferrite bead and a separate LDO. Match differential clock traces to 100 ohm differential impedance with length matching to within 5 mils. Place a 0.1 uF AC-coupling capacitor within 100 mils of each transceiver pin pair.
Estimated: The EP1AGX35DF780C6N can dissipate up to approximately 8 W with all 8 transceivers active at 3.125 Gbps and high logic utilization. The FC-FBGA package relies on the PCB thermal land and the top-side spreader; a minimum 6-layer board with thermal vias (0.3 mm pitch) under the package is recommended for unrestricted operation. Without forced airflow, derate transceiver throughput or reduce LE utilization to stay below junction 100C at 70C ambient.
Estimated: Quartus II 13.1 is the last version with reliable support for the Arria GX family. Newer Quartus Prime releases (15.0 and later) drop Arria GX device support, locking legacy designs into an obsolete toolchain. Plan migration to Arria V or Arria 10 using Quartus Prime's 'Project Migration' wizard; expect 80-90% porting effort and verify transceiver IP core changes (Altera's MegaWizard is replaced by IP Catalog in newer releases).
Compliance Information
Lead-free 780-ball FC-FBGA per FindIC package data. Halogen-free status not explicitly stated in verified data - set to 'unknown'. RoHS and REACH compliance per Altera/Intel product environmental certification. Not AEC-Q100 qualified - this is a commercial-grade FPGA, not an automotive part.
