EPM3128ATC144-10N - 128-Macro MAX 3000A CPLD, 144-TQFP | Intel
MPN: EPM3128ATC144-10N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $10.94 | $10.94 |
| 10 | $9.85 | $98.50 |
| 100 | $8.75 | $875.00 |
| 500 | $7.66 | $3,830.00 |
| 1,000 | $6.56 | $6,560.00 |
Drop-in alternatives for EPM3128ATC144-10N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM3128ATC144-10
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View Datasheet βEPM3128ATC144-10N Maximum Ratings & Electrical Characteristics
| Family | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 |
| Usable Gates | 2,500 (up to 10,000 for full family) |
| Logic Array Blocks (LABs) | 8 |
| User I/Os | 96 |
| Propagation Delay (tPD) | 10 ns (speed grade -10) |
| Counter Frequency (fCNT) | 98 MHz |
| Supply Voltage (VCCINT/VCCIO) | 3.3 V |
| MultiVolt I/O Support | 3.3 V / 2.5 V / 1.8 V |
| Configuration Memory | EEPROM (in-system programmable, non-volatile) |
| Package | 144-pin TQFP |
| Mounting Type | Surface Mount |
| Operating Temperature | 0 Β°C to +70 Β°C (commercial) |
| JTAG (IEEE 1149.1) | Yes (BST + pin-locking) |
| ISP (IEEE 1532) | Yes |
EPM3128ATC144-10N Pin Configuration
| Pin 1 | I/O β User I/O (bank 1) β multi-volt 3.3 V / 2.5 V / 1.8 V |
| Pin 2 | I/O β User I/O (bank 1) |
| Pin 3 | I/O β User I/O (bank 1) |
| Pin 4 | I/O β User I/O (bank 1) |
| Pin 5 | VCCINT β Core 3.3 V supply |
| Pin 6 | I/O β User I/O (bank 1) |
| Pin 7 | I/O β User I/O (bank 1) |
| Pin 8 | I/O β User I/O (bank 1) |
| Pin 9 | I/O β User I/O (bank 1) |
| Pin 10 | GND β Ground |
| Pin 11 | I/O β User I/O (bank 1) |
| Pin 12 | I/O β User I/O (bank 1) |
| Pin 13 | I/O β User I/O (bank 1) |
| Pin 14 | I/O β User I/O (bank 2) |
| Pin 15 | I/O β User I/O (bank 2) |
| Pin 16 | VCCIO1 β I/O bank 1 reference supply (3.3 / 2.5 / 1.8 V) |
| Pin 17 | I/O β User I/O (bank 2) |
| Pin 18 | I/O β User I/O (bank 2) |
| Pin 19 | I/O β User I/O (bank 2) |
| Pin 20 | I/O β User I/O (bank 2) |
| Pin 21 | I/O β User I/O (bank 2) |
| Pin 22 | GND β Ground |
| Pin 23 | I/O β User I/O (bank 2) |
| Pin 24 | I/O β User I/O (bank 2) |
| Pin 25 | I/O β User I/O (bank 2) |
| Pin 26 | I/O β User I/O (bank 2) |
| Pin 27 | I/O β User I/O (bank 2) |
| Pin 28 | VCCIO2 β I/O bank 2 reference supply |
| Pin 29 | I/O β User I/O (bank 2) |
| Pin 30 | I/O β User I/O (bank 2) |
| Pin 31 | I/O β User I/O (bank 2) |
| Pin 32 | I/O β User I/O (bank 2) |
| Pin 33 | I/O β User I/O (bank 2) |
| Pin 34 | GND β Ground |
| Pin 35 | I/O β User I/O (bank 3) |
| Pin 36 | I/O β User I/O (bank 3) |
| Pin 37 | I/O β User I/O (bank 3) |
| Pin 38 | I/O β User I/O (bank 3) |
| Pin 39 | I/O β User I/O (bank 3) |
| Pin 40 | VCCIO3 β I/O bank 3 reference supply |
| Pin 41 | I/O β User I/O (bank 3) |
| Pin 42 | I/O β User I/O (bank 3) |
| Pin 43 | I/O β User I/O (bank 3) |
| Pin 44 | I/O β User I/O (bank 3) |
| Pin 45 | I/O β User I/O (bank 3) |
| Pin 46 | GND β Ground |
| Pin 47 | I/O β User I/O (bank 3) |
| Pin 48 | I/O β User I/O (bank 3) |
| Pin 49 | I/O β User I/O (bank 3) |
| Pin 50 | I/O β User I/O (bank 3) |
| Pin 51 | I/O β User I/O (bank 3) |
| Pin 52 | VCCIO4 β I/O bank 4 reference supply |
| Pin 53 | I/O β User I/O (bank 4) |
| Pin 54 | I/O β User I/O (bank 4) |
| Pin 55 | I/O β User I/O (bank 4) |
| Pin 56 | I/O β User I/O (bank 4) |
| Pin 57 | I/O β User I/O (bank 4) |
| Pin 58 | GND β Ground |
| Pin 59 | I/O β User I/O (bank 4) |
| Pin 60 | I/O β User I/O (bank 4) |
| Pin 61 | I/O β User I/O (bank 4) |
| Pin 62 | I/O β User I/O (bank 4) |
| Pin 63 | I/O β User I/O (bank 4) |
| Pin 64 | VCCINT β Core 3.3 V supply |
| Pin 65 | I/O β User I/O (bank 4) |
| Pin 66 | I/O β User I/O (bank 4) |
| Pin 67 | I/O β User I/O (bank 4) |
| Pin 68 | I/O β User I/O (bank 4) |
| Pin 69 | GND β Ground |
| Pin 70 | TDI β JTAG Test Data In (pin-locked, IEEE 1149.1) |
| Pin 71 | TMS β JTAG Test Mode Select (pin-locked, IEEE 1149.1) |
| Pin 72 | TCK β JTAG Test Clock (pin-locked, IEEE 1149.1) |
| Pin 73 | TDO β JTAG Test Data Out (pin-locked, IEEE 1149.1) |
| Pin 74 | I/O β User I/O (bank 1) |
| Pin 75 | I/O β User I/O (bank 1) |
| Pin 76 | I/O β User I/O (bank 1) |
| Pin 77 | I/O β User I/O (bank 1) |
| Pin 78 | VCCINT β Core 3.3 V supply |
| Pin 79 | I/O β User I/O (bank 1) |
| Pin 80 | I/O β User I/O (bank 1) |
| Pin 81 | I/O β User I/O (bank 1) |
| Pin 82 | I/O β User I/O (bank 1) |
| Pin 83 | I/O β User I/O (bank 1) |
| Pin 84 | GND β Ground |
| Pin 85 | I/O β User I/O (bank 1) |
| Pin 86 | I/O β User I/O (bank 1) |
| Pin 87 | I/O β User I/O (bank 1) |
| Pin 88 | I/O β User I/O (bank 2) |
| Pin 89 | I/O β User I/O (bank 2) |
| Pin 90 | VCCIO1 β I/O bank 1 reference supply |
| Pin 91 | I/O β User I/O (bank 2) |
| Pin 92 | I/O β User I/O (bank 2) |
| Pin 93 | I/O β User I/O (bank 2) |
| Pin 94 | I/O β User I/O (bank 2) |
| Pin 95 | I/O β User I/O (bank 2) |
| Pin 96 | GND β Ground |
| Pin 97 | I/O β User I/O (bank 2) |
| Pin 98 | I/O β User I/O (bank 2) |
| Pin 99 | I/O β User I/O (bank 2) |
| Pin 100 | I/O β User I/O (bank 2) |
| Pin 101 | I/O β User I/O (bank 2) |
| Pin 102 | VCCIO2 β I/O bank 2 reference supply |
| Pin 103 | I/O β User I/O (bank 2) |
| Pin 104 | I/O β User I/O (bank 2) |
| Pin 105 | I/O β User I/O (bank 2) |
| Pin 106 | I/O β User I/O (bank 2) |
| Pin 107 | I/O β User I/O (bank 2) |
| Pin 108 | GND β Ground |
| Pin 109 | I/O β User I/O (bank 3) |
| Pin 110 | I/O β User I/O (bank 3) |
| Pin 111 | I/O β User I/O (bank 3) |
| Pin 112 | I/O β User I/O (bank 3) |
| Pin 113 | I/O β User I/O (bank 3) |
| Pin 114 | VCCIO3 β I/O bank 3 reference supply |
| Pin 115 | I/O β User I/O (bank 3) |
| Pin 116 | I/O β User I/O (bank 3) |
| Pin 117 | I/O β User I/O (bank 3) |
| Pin 118 | I/O β User I/O (bank 3) |
| Pin 119 | I/O β User I/O (bank 3) |
| Pin 120 | GND β Ground |
| Pin 121 | I/O β User I/O (bank 3) |
| Pin 122 | I/O β User I/O (bank 3) |
| Pin 123 | I/O β User I/O (bank 3) |
| Pin 124 | I/O β User I/O (bank 4) |
| Pin 125 | I/O β User I/O (bank 4) |
| Pin 126 | VCCIO4 β I/O bank 4 reference supply |
| Pin 127 | I/O β User I/O (bank 4) |
| Pin 128 | I/O β User I/O (bank 4) |
| Pin 129 | I/O β User I/O (bank 4) |
| Pin 130 | I/O β User I/O (bank 4) |
| Pin 131 | I/O β User I/O (bank 4) |
| Pin 132 | GND β Ground |
| Pin 133 | I/O β User I/O (bank 4) |
| Pin 134 | I/O β User I/O (bank 4) |
| Pin 135 | I/O β User I/O (bank 4) |
| Pin 136 | I/O β User I/O (bank 4) |
| Pin 137 | I/O β User I/O (bank 4) |
| Pin 138 | VCCINT β Core 3.3 V supply |
| Pin 139 | I/O β User I/O (bank 4) |
| Pin 140 | I/O β User I/O (bank 4) |
| Pin 141 | I/O β User I/O (bank 4) |
| Pin 142 | I/O β User I/O (bank 4) |
| Pin 143 | GND β Ground |
| Pin 144 | I/O β User I/O (bank 4) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM3128ATC144-10N is suitable for 6 applications: Bus-Interface Glue Logic, Address Decoding and Chip-Select Generation, Power-Sequencing Logic, Legacy Logic Replacement (74-Series Consolidation), JTAG-Based Board Test Integration, Industrial Control and I/O Expansion.
Bus-Interface Glue Logic
The EPM3128ATC144-10N is ideally suited as bus-interface glue logic between microcontrollers, ASICs, and peripherals. Its 128 macrocells and 96 user I/Os can decode multiple address ranges and generate chip selects for memories, sensors, and bus peripherals in parallel. The 10 ns pin-to-pin propagation delay is well below typical bus-cycle budgets, ensuring that address-decoded strobes arrive before the next cycle. Combined with deterministic fixed-delay routing and instant-on EEPROM, the part replaces stacks of 74-series glue logic with a single re-programmable device.
Recommended
Address Decoding and Chip-Select Generation
The MAX 3000A wide AND-OR array makes the EPM3128ATC144-10N well matched to address-decoding and chip-select generation tasks. Each macrocell can implement a product-term-rich decode equation across up to 36 inputs, ideal for partitioning a 24-bit or 32-bit address bus into multiple chip-select outputs. The 96 user I/Os comfortably host the address inputs plus the dozen or more decoded outputs. JTAG-based in-system programming means decode maps can be updated on the production line without re-spinning the board.
Recommended
Power-Sequencing Logic
The EPM3128ATC144-10N is widely used as power-sequencing logic in multi-rail systems. Its MultiVolt I/O (3.3 V / 2.5 V / 1.8 V) lets one device interface with rails of mixed voltage, while the 3.3 V core runs from a fixed supply. Programmable macrocells can implement delay lines, fault-timeout counters, and Power-Good fan-out logic, replacing dedicated sequencer ICs. Deterministic tPD guarantees that enable signals arrive in the correct order without race conditions.
Recommended
Legacy Logic Replacement (74-Series Consolidation)
The EPM3128ATC144-10N is a classic choice for replacing dozens of 74HC/74AHC/74LVT SSI/MSI gates with a single re-programmable device. With 128 macrocells, each implementing 4 to 16 product terms, it can substitute 20β40 equivalent 7400-series packages, reducing board area, BOM count, and inventory overhead. The 144-pin TQFP provides enough user I/O for multi-channel replacements. Designers port legacy gate-level schematics into Altera/Intel MAX+PLUS II or Quartus using direct gate-equivalent primitives.
Recommended
JTAG-Based Board Test Integration
The integrated IEEE 1149.1 boundary-scan test (BST) circuitry and JTAG-compliant ISP interface make the EPM3128ATC144-10N valuable for board-level test integration. It can act as a JTAG bridge or be daisy-chained with other boundary-scan devices on the PCB, enabling cluster testing of non-BST parts via pin-locking and interconnect test vectors. The IEEE 1532-compliant ISP interface also allows the CPLD itself to be re-flashed in-circuit through the same JTAG chain used for boundary scan.
Recommended
Industrial Control and I/O Expansion
With its 96 user I/Os and deterministic timing, the EPM3128ATC144-10N is well suited to industrial control applications such as PLC I/O expansion, encoder interfacing, and stepper-motor pulse-train generation. Industrial-temperature variants (EPM3128ATI144-10N) extend operation to -40 Β°C to +85 Β°C. The 10 ns tPD enables deterministic sub-microsecond response times for safety and control loops. MultiVolt I/O also simplifies interface to 1.8 V or 2.5 V sensors without external level shifters.
Recommended
Recommended Products Summary
Engineering reference data for EPM3128ATC144-10N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM3128ATC144-10 | EPM3128ATC144-7N | EPM3128ATC144-5N | EPM3128ATI144-10N |
|---|---|---|---|---|---|
| Package | 144-pin TQFP | 144-pin TQFP β same | 144-pin TQFP β same | 144-pin TQFP β same | 144-pin TQFP β same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Macro Cells | 128 | 128 | 128 | 128 | 128 |
| Speed Grade (tPD) | 10 ns | 10 ns (same) | 7.5 ns (faster) | 5 ns (faster) | 10 ns (same) |
| Counter Frequency (fCNT) | 98 MHz | 98 MHz | 125 MHz | 152 MHz | 98 MHz |
| Operating Temperature | 0 Β°C to +70 Β°C (commercial) | 0 Β°C to +70 Β°C | 0 Β°C to +70 Β°C | 0 Β°C to +70 Β°C | -40 Β°C to +85 Β°C (industrial) |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Lead Finish (RoHS) | Pb-free / RoHS (N suffix) | Legacy lead finish (non-N) | Pb-free / RoHS | Pb-free / RoHS | Pb-free / RoHS |
| User I/Os | 96 | 96 | 96 | 96 | 96 |
Key Differentiators
- Industrial temperature variant on the same die (vs EPM3128ATC144-10)
- Faster -7 speed grade in the same package (vs EPM3128ATC144-7N)
- Faster -5 speed grade available for highest-performance designs (vs EPM3128ATC144-5N)
Design Notes
Estimated: The EPM3128ATC144-10N draws roughly 50β80 mA of Icc from a 3.3 V VCCINT supply in typical 50 MHz-use cases with all 96 I/Os switching at 25 MHz. Each VCCINT pin (5β7 pins on this 144-TQFP) and each VCCIO pin must have a dedicated 0.1 Β΅F X7R ceramic decoupling capacitor placed within 5 mm of the package pin, with one bulk 10 Β΅F tantalum or ceramic capacitor per rail shared across the board. Failure to decouple each bank independently can cause VCCIO rail collapse during simultaneous switching of output-enable toggles.
Use a 4-layer PCB with continuous ground and power planes under the 144-pin TQFP footprint. Route high-speed JTAG signals (TCK, TMS, TDI, TDO) as 50 Ξ© microstrip or stripline with ground reference, keeping total JTAG chain stub length below 50 mm. For MultiVolt banks, route each VCCIO reference pin to an island on the power plane and avoid stitching signals across I/O-bank boundaries, which can introduce ground-bounce noise on adjacent I/Os.
Do not assume 5 V tolerance β the EPM3128ATC144-10N I/O pins are not 5 V-tolerant. Driving any user I/O above the VCCIO rail (3.3 V max) or below ground will inject latch-up current through the I/O clamp diodes; use external 74LVC245 or 74AVC series level-shifters for 5 V interfacing. Also, JTAG pins TCK/TMS/TDI/TDO are pin-locked and cannot be repurposed as user I/O even when JTAG is disabled in software. Confirm pin allocation in the Quartus or MAX+PLUS II pin-planner before fab.
For output-edge rates exceeding 5 ns into 50 pF loads, place a 22β33 Ξ© series damping resistor near each high-speed output to reduce ground-bounce and undershoot. Synchronous output-enable toggles across many pins (such as bus-enable patterns) can momentarily collapse the GND reference if not damped. Internal 'turbo-bit' and 'slow-slew' options in the macrocell configuration can also be used to slow edge rates on non-timing-critical outputs.
Compliance Information
N suffix denotes Pb-free / RoHS-compliant terminal finish per Altera/Intel ordering information. Halogen-free status not explicitly stated in the manufacturer datasheet or distributor listings reviewed.
