EP1SGX10DF672I6 - Stratix GX FPGA, 10570 LEs, 672-FBGA | Intel
MPN: EP1SGX10DF672I6 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $396 | $396.00 |
| 10 | $370 | $3,700.00 |
| 25 | $350 | $8,750.00 |
| 100 | $320 | $32,000.00 |
| 500 | $290 | $145,000.00 |
Drop-in alternatives for EP1SGX10DF672I6 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EP1SGX10DF672C7N
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View Datasheet →EP1SGX10DF672C7
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View Datasheet →EP1SGX10DF672C6N
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View Datasheet →EP1SGX10DF672C5N
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View Datasheet →EP1SGX10CF672C7N
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View Datasheet →EP1SGX10DF672I6 Maximum Ratings & Electrical Characteristics
| Family | Stratix GX |
| Logic Elements (LEs) | 10,570 |
| Embedded RAM | 920,448 bits |
| Embedded Multipliers | Yes (DSP blocks) |
| Transceiver Channels | 12 (3.125 Gbps) |
| Maximum User I/O | 362 |
| PLLs | 4 |
| Process Technology | 130 nm CMOS |
| Core Supply Voltage | 1.5 V |
| Operating Temperature | 0 C to +85 C (commercial) |
| Package | 672-ball FC-FBGA (DF672) |
| Package Body Size | 33 x 33 mm, 1.0 mm pitch |
| Mounting Type | Surface Mount |
EP1SGX10DF672I6 33 x 33 mm, 1.0 mm pitch Pin Configuration Guide
Complete pinout information for EP1SGX10DF672I6 (33 x 33 mm, 1.0 mm pitch package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1SGX10DF672I6.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1SGX10DF672I6 is suitable for 6 applications: Multi-Gigabit Serial Backplane Interface, SONET/SDH and Fibre Channel Equipment, ASIC Prototyping and Emulation, Custom SERDES-Based Protocol Bridges, High-Throughput Data Acquisition Front End, Industrial Imaging and Broadcast Video Processing.
Multi-Gigabit Serial Backplane Interface
The EP1SGX10DF672I6's 12 integrated 3.125 Gbps transceiver channels and 362 user I/O pins make it a strong fit for multi-gigabit serial backplane interfaces such as ATCA, SerialLite II, and custom SERDES-based fabric cards. Each channel provides hardened PMA/PCS blocks that bypass the latency and BOM cost of an external PHY, while the 10,570-LE fabric comfortably absorbs custom protocol framing, error correction, and routing logic. Designers place the device on a controlled-impedance stack-up with separate analog/digital transceiver planes, using the four on-chip PLLs to derive the required reference clocks. Compared with a discrete SERDES-plus-ASIC solution, the integrated transceivers reduce board area and ease timing closure for 2.5 Gbps and 3.125 Gbps links.
Recommended
SONET/SDH and Fibre Channel Equipment
Telecom and storage OEMs adopted the EP1SGX10DF672I6 for OC-48 (2.488 Gbps) SONET/SDH line cards and 1G/2G Fibre Channel controllers, where its transceiver block delivers deterministic jitter performance and the TriMatrix memory absorbs pointer-adjustment FIFOs. The 920448-bit embedded RAM allows multi-frame buffering without external SRAM, while 4 PLLs cover the SONET stratum timing and Fibre Channel oversampling clocks. The device is specified over the commercial 0 C to +85 C range that suits controlled-environment central-office racks. Quartus II MegaCores (ALT2GXB, SONET framer) accelerate compliance work and shorten development cycles for these legacy telecom protocols.
Recommended
ASIC Prototyping and Emulation
ASIC prototyping teams use the EP1SGX10DF672I6 to validate RTL before committing a mask, leveraging the 10,570 logic elements and 362 I/O to map medium-complexity ASIC blocks such as custom CPUs, DSP pipelines, or peripheral controllers. The 130 nm Stratix GX fabric provides predictable timing for multi-million-cycle regressions, and the FC-FBGA package supports fast bring-up on a TDM-style prototype board. Quartus II integrates with third-party synthesis (Synopsys Design Compiler, Mentor Precision) and supports deep trace buffers for debugging. Compared with FPGAs of the era, the Stratix GX's embedded transceivers let ASIC teams reproduce SERDES interfaces on the same prototype board, avoiding two-step verification.
Recommended
Custom SERDES-Based Protocol Bridges
Industrial and broadcast OEMs built custom protocol bridges (Aurora, SerialLite, custom LVDS-to-SERDES, HD-SDI expansions) on the EP1SGX10DF672I6, using the 12 transceiver channels as configurable SERDES and the LAB fabric to implement link-layer adaptation, scrambling, and clock-domain crossing. With 920448 bits of block RAM and dedicated DSP blocks, the device handles encryption, scrambling, and real-time video processing alongside the SERDES logic. The DF672 package's 1.0 mm pitch supports compact multi-channel designs, and the industrial temperature screen suits factory-floor equipment. Quartus II ALT2GXB and Aurora megacores shorten bridge bring-up to weeks rather than months.
Recommended
High-Throughput Data Acquisition Front End
The EP1SGX10DF672I6 suits high-throughput data acquisition front ends used in test & measurement, radar digitizers, and medical imaging, where ADC samples stream into the FPGA at hundreds of MHz and must be pre-processed, packetised, and shipped off-board over multiple 3.125 Gbps serial links. The 362 user I/O pins absorb wide parallel LVDS buses from external ADCs, while the 12 transceivers aggregate the pre-processed data onto 10G-class uplinks. Quartus II's SignalTap and SystemConsole tools let engineers correlate front-end stimuli with internal state, an essential capability when validating measurement IP. The 1.5 V core supply keeps dynamic power manageable for densely populated acquisition cards.
Recommended
Industrial Imaging and Broadcast Video Processing
The EP1SGX10DF672I6 is well matched to industrial imaging and broadcast video pipelines, including HD-SDI expansion, video-over-IP gateways, and machine-vision preprocessing. The 362 I/O pins accept multi-channel Camera Link or HDMI input bridges, the 12 transceivers aggregate outputs onto 3G-SDI or 10G Ethernet, and the DSP blocks accelerate colour-space conversion and chroma resampling. Designers rely on Quartus II video megacores and the Stratix GX Device Handbook's transceiver reference designs to meet broadcast-grade jitter masks. The DF672 FC-FBGA package simplifies thermal management in 1U broadcast frames, and the 0 C to +85 C screen suits both controlled studio racks and industrial enclosures.
Recommended
Recommended Products Summary
Engineering reference data for EP1SGX10DF672I6 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1SGX10DF672C7N | EP1SGX10DF672C7 | EP1SGX10DF672C6N | EP1SGX10DF672C5N | EP1SGX10CF672C7N |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | 672-ball FC-FBGA (DF672) | 672-ball FC-FBGA (DF672) - same | 672-ball FC-FBGA (DF672) - same | 672-ball FC-FBGA (DF672) - same | 672-ball FC-FBGA (DF672) - same | 672-ball FC-FBGA (CF672) - different pinout |
| Logic Elements | 10,570 | 10,570 | 10,570 | 10,570 | 10,570 | 10,570 |
| Embedded RAM | 920,448 bits | 920,448 bits | 920,448 bits | 920,448 bits | 920,448 bits | 920,448 bits |
| Transceiver Channels | 12 x 3.125 Gbps | 12 x 3.125 Gbps | 12 x 3.125 Gbps | 12 x 3.125 Gbps | 12 x 3.125 Gbps | 12 x 3.125 Gbps |
| Speed Grade | -6 (industrial) | -7 (commercial) | -7 (commercial) | -6 (commercial) | -5 (commercial) | -7 (commercial) |
| Operating Temperature | 0 C to +85 C (commercial bin) | 0 C to +85 C | 0 C to +85 C | 0 C to +85 C | 0 C to +85 C | 0 C to +85 C |
| Process Technology | 130 nm CMOS | 130 nm CMOS | 130 nm CMOS | 130 nm CMOS | 130 nm CMOS | 130 nm CMOS |
| Pin/Ball Count | 672 | 672 | 672 | 672 | 672 | 672 |
Key Differentiators
- Integrated 3.125 Gbps transceivers eliminate external SERDES PHY cost and latency (vs EP1S10F672C7N)
- Industrial-speed-grade bin at -6 timing (vs EP1SGX10DF672C7N)
- 920448-bit TriMatrix memory absorbs multi-frame buffering without external SRAM (vs EP1S10F672C7N)
- 672-ball FC-FBGA at 1.0 mm pitch eases PCB escape vs 1020-ball BGA variants (vs EP1SGX25DF1020C7)
Design Notes
Estimated: the EP1SGX10DF672I6 core supply is 1.5 V with separate VCCPD, VCCIO, VCCA_PLL, and VCCA_TX/RX rails. For a design using 80% LEs at 200 MHz and all 12 transceivers active at 3.125 Gbps, total board-level power is typically 5 W to 8 W; allocate at least 4 bulk-decoupling 220 uF polymer caps on the 1.5 V plane, and place 0.1 uF + 0.01 uF ceramic pairs within 100 mils of every VCC pin pair. The transceiver analog supply must be sourced from a low-noise LDO (e.g., LTM8023) with a pi-filter, never shared with switching digital rails.
The 672-ball FC-FBGA uses a 1.0 mm pitch and a 33 x 33 mm body, so PCB stack-up must support laser-drilled microvias with 4 mil capture pads and a 6/6 mil trace/space geometry on the top layers. Implement a 6-layer stack-up (top: signal/GND, inner1: GND, inner2: power, inner3: power, inner4: GND, bottom: signal/GND) with continuous reference planes under the BGA fan-out. Add a copper coin or 1-oz pour directly beneath the package exposed-pad region to spread heat; without this, junction temperature can exceed 100 C in a still-air enclosure.
Keep transceiver TX/RX pairs within 250 mils of the edge of the FC-FBGA and route them on the top microstrip layer with a continuous reference plane below; never route TX and RX lanes across a plane split. Each transceiver lane requires a 100-ohm differential impedance with intra-pair skew below 1 ps; use length matching within 5 mils for the TX pair and 5 mils for the RX pair. Place the reference-clock oscillator within 500 mils of the dedicated CLK input pins and guard it with a ground moat to isolate it from digital switching noise.
Use HyperLynx or ANSYS SIwave to simulate the 672-ball breakout before fabrication. Critical nets to model are the 12 transceiver channels (100-ohm differential, 3.125 Gbps), the global clock trees (which feed the PLLs and the LAB clock networks), and the LVDS I/O buses if used for camera-link or memory interfaces. Return loss for the transceiver channels should be below -10 dB at 1.5 GHz; if simulation shows resonance near Nyquist, add a small series-damping resistor (4.7 ohm to 10 ohm) at the TX driver output.
A common pitfall when migrating from the EP1SGX10DF672I6 to the EP1SGX10CF672C7N is assuming the DF672 and CF672 ball maps are interchangeable - they are not, even though both are 672-ball FC-FBGA. Verify the Quartus II pinout file for each suffix before PCB rework. Another pitfall is leaving the CONFIG_DONE pin floating: the Stratix GX requires CONFIG_DONE to be pulled high through a 1 kohm to 10 kohm resistor so the configuration controller releases the I/O buffers cleanly after bitstream load.
Compliance Information
RoHS, REACH, lead-free, and halogen-free status for the EP1SGX10DF672I6 were not provided in the verified web data; set to 'unknown' pending an Intel/Altera product page update. AEC-Q100 is not applicable because this is an FPGA not an automotive-grade IC. The part is in the obsolete lifecycle phase per Intel's product-discontinuance policy for mature Stratix GX devices.
