EP20K1000CF672I9 - APEX 20KC 1M-Gate FPGA, 672-BGA | Intel
MPN: EP20K1000CF672I9 ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $265.5 | $2,655.00 |
| 100 | $240 | $24,000.00 |
| 500 | $218.4 | $109,200.00 |
| 1,000 | $195 | $195,000.00 |
Drop-in alternatives for EP20K1000CF672I9 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EP20K1000CF672I8N
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View Datasheet →EP20K1000CF672I8
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View Datasheet →EP20K1000CF672I7
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View Datasheet →EP20K1000CF672C9N
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View Datasheet →EP20K1000CF672C9ES
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View Datasheet →EP20K1000CF672C8N
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View Datasheet →EP20K1000CF672I9 Maximum Ratings & Electrical Characteristics
| Family | APEX 20KC |
| Typical Gates | 1,000,000 |
| Logic Elements (LEs) | 38,400 |
| Maximum User I/O | 508 |
| Dedicated Inputs | 4 |
| Embedded System Blocks (ESBs) | Available (RAM/ROM/CAM) |
| Core Voltage | 1.71 V to 1.89 V (1.8 V nominal) |
| Process Technology | 0.15 µm CMOS, SRAM-based |
| Internal Performance | 250 MHz |
| Operating Temperature | -40 °C to +85 °C (industrial) |
| Package | 672-ball FC-FBGA (FineLine BGA) |
| Mounting Type | Surface Mount (BGA) |
| MultiVolt I/O Support | 1.8 V / 2.5 V / 3.3 V / 5.0 V |
| Speed Grade | I (industrial, 9 suffix) |
| Configuration Method | SRAM (volatile, requires config device) |
EP20K1000CF672I9 672-ball fc-fbga (fineline bga) Pin Configuration Guide
Complete pinout information for EP20K1000CF672I9 (672-ball fc-fbga (fineline bga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K1000CF672I9.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP20K1000CF672I9 is suitable for 6 applications: Telecom Backplane Interface, DSP Co-Processing Card, Industrial Control / Factory Automation, ASIC Prototyping, Multi-Channel Protocol Converter, Legacy Networking Line Card.
Telecom Backplane Interface
The EP20K1000CF672I9 fits telecom backplane bridging because its 1,000,000 system gates and 38,400 LEs can absorb wide parallel bus protocols and serial-to-parallel conversion logic on a single device. The 508 user I/O plus MultiVolt support lets it bridge 5 V legacy bus transceivers to 3.3 V / 2.5 V framers without external level shifters. Embedded System Blocks configured as dual-port RAM provide 540 Kibits of packet buffering, while the 250 MHz internal performance sustains 100+ MHz wide-bus throughput. Designers place the device between line-card PHY ASICs and the switch-fabric backplane, with JTAG for in-system reprogrammability.
Recommended
DSP Co-Processing Card
The EP20K1000CF672I9 is well-suited for DSP co-processing boards where host DSPs offload FIR/FFT pipelines. Its 38,400 LEs implement hundreds of 18x18 multipliers as soft logic, and the 250 MHz internal performance supports 100 MHz datapath clocks. The 1.8 V core plus MultiVolt I/O lets the FPGA connect directly to 3.3 V DSP host buses. Embedded System Blocks deliver zero-wait-state scratch RAM for coefficient storage. The 672-ball FC-FBGA provides enough I/O to expose dual 64-bit host ports plus four serial RapidIO links, fitting VME/CompactPCI payload cards.
Recommended
Industrial Control / Factory Automation
The EP20K1000CF672I9 supports factory-automation controllers with its industrial -40 °C to +85 °C temperature range and high I/O count for multi-axis motor control. Its 38,400 LEs implement up to 12 PID loops, encoder counters, and fieldbus protocol stacks (Profibus, CANopen) on one device. The 508 I/O drive 5 V optocoupler interfaces directly via MultiVolt without level shifters, simplifying safety-isolated designs. The 672-ball FC-FBGA withstands industrial vibration environments better than QFP. Legacy factories keep this part in service because long-running PLC programs are tied to APEX 20KC bitstreams.
Recommended
ASIC Prototyping
The EP20K1000CF672I9 is commonly used for ASIC prototyping where designers map million-gate ASICs into a single FPGA for pre-silicon validation. Its 1,000,000 typical gates accommodate medium-complexity SoCs, and the SRAM-based fabric allows rapid RTL revisions. Embedded System Blocks model SRAM macros, dual-port register files, and CAMs that ASIC designers expect to see at-speed. MultiVolt I/O bridges 5 V / 3.3 V / 1.8 V ASIC pad libraries to standard testbench instrumentation. The 672-ball FC-FBGA exposes enough I/O for full ASIC-pin visibility plus JTAG and trace ports.
Recommended
Multi-Channel Protocol Converter
The EP20K1000CF672I9 fits protocol-converter cards that bridge UART, SPI, I2C, and parallel buses to Ethernet or USB. Its 38,400 LEs implement multiple soft-core CPUs (Nios or custom), while the 508 I/O fan out to dozens of peripheral channels. Embedded System Blocks configured as FIFOs decouple channels with different clock domains. MultiVolt I/O lets one FPGA interface both 5 V RS-232 transceivers and 3.3 V / 1.8 V application processors. The industrial temperature grade makes it suitable for outdoor telecom and transportation protocol-conversion boxes.
Recommended
Legacy Networking Line Card
The EP20K1000CF672I9 powers legacy router and switch line cards where the original design used APEX 20KC and the OEM needs lifecycle support. Its 1,000,000 gates implement forwarding engines, ACL tables, and queue managers, while 508 I/O connect to PHY chips and switch fabric ASICs. MultiVolt I/O bridges 5 V / 3.3 V legacy PHYs to 2.5 V fabric ASICs. The 672-ball FC-FBGA fits the original line-card footprint, eliminating the need for board rework. The SRAM fabric is in-system reprogrammable, so network operators can field-upgrade bitstreams without RMA.
Recommended
Recommended Products Summary
Engineering reference data for EP20K1000CF672I9 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K1000CF672I8N | EP20K1000CF672I8 | EP20K1000CF672I7 | EP20K1000CF672C9N | EP20K1000CF672C9ES | EP20K1000CF672C8N |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 672-ball FC-FBGA | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same |
| Logic Elements | 38,400 | 38,400 | 38,400 | 38,400 | 38,400 | 38,400 | 38,400 |
| Typical System Gates | 1,000,000 | 1,000,000 | 1,000,000 | 1,000,000 | 1,000,000 | 1,000,000 | 1,000,000 |
| Speed Grade | I9 (industrial, fastest I-grade) | I8 (slower than I9 by ~5%) | I8 (slower than I9 by ~5%) | I7 (slower than I9 by ~10%) | C9 (matches I9 timing) | C9 ES variant | C8 (slower than I9 by ~5%) |
| Operating Temperature | -40 °C to +85 °C (industrial) | -40 °C to +85 °C (industrial) | -40 °C to +85 °C (industrial) | -40 °C to +85 °C (industrial) | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (commercial) |
| Core Voltage | 1.71 V to 1.89 V (1.8 V nominal) | 1.71 V to 1.89 V | 1.71 V to 1.89 V | 1.71 V to 1.89 V | 1.71 V to 1.89 V | 1.71 V to 1.89 V | 1.71 V to 1.89 V |
| Lifecycle Status (2026-09-07) | Last-Time-Buy | Obsolete (older speed grade) | Obsolete (older speed grade) | Obsolete (oldest industrial grade) | Obsolete (commercial) | Obsolete (engineering sample) | Obsolete (commercial) |
| Price (1 pc, USD, as of 2026-09-07) | 285.00 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- I9 speed grade = fastest industrial-grade timing in the APEX 20KC 1M family (vs EP20K1000CF672I8N)
- Industrial -40 °C to +85 °C temperature range (vs 0 °C to +85 °C commercial) (vs EP20K1000CF672C9N)
- 1,000,000 typical gates - highest density in the APEX 20KC 672-ball family (vs EP20K1000CF672C7GZ)
Design Notes
The EP20K1000CF672I9 requires a 1.8 V core rail plus one or more I/O bank voltages (1.8 V / 2.5 V / 3.3 V / 5.0 V via MultiVolt). Power sequencing must follow Altera AN-114: bring up VCCINT (1.8 V core) before or simultaneously with VCCIO banks. A bulk 220 µF tantalum plus 10 µF ceramic decoupling near each supply pin suppresses FPGA inrush transients during configuration. Estimated core current at 250 MHz with 100% utilization is 1.5-2 A; design the 1.8 V regulator for 3 A peak for margin.
The 672-ball FC-FBGA at 1.0 mm pitch requires a 4-6 layer PCB with microvia escape. Per Altera AN-114, fan-out the BGA with 8-mil via-in-pad microvias on the top layer and route signals on inner layers. Provide a continuous ground plane under the device to control return paths for 100+ MHz LVTTL signals. JTAG pins (TCK, TMS, TDI, TDO, TRST) must be brought out to a 2x5 or 1x10 header for in-system programming with a ByteBlaster or USB-Blaster download cable.
Estimated: APEX 20KC devices use SRAM-based configuration, so the bitstream is volatile - the device loses configuration on power-down and must be reloaded from a configuration EPROM (EPC16 or EPC2) on each power-up. Do not leave MSEL pins floating - they select configuration mode (AS, AP, PS, JTAG) and incorrect strapping leaves the device in an undefined state. The CONF_DONE pin must be pulled high with a 10 kΩ resistor and monitored by the system reset logic.
Compliance Information
RoHS/REACH/lead-free status not specified in the verified web data for EP20K1000CF672I9; the APEX 20KC family predates widespread RoHS adoption, so many variants are non-RoHS. AEC-Q100 is not applicable because the device is a general-purpose FPGA, not an automotive-grade IC.
