EP20K1000CF672C9N - APEX 20KC 1M Gates FPGA | Intel / Altera
MPN: EP20K1000CF672C9N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $255 | $2,550.00 |
| 100 | $215 | $21,500.00 |
| 500 | $188 | $94,000.00 |
| 1,000 | $165 | $165,000.00 |
Drop-in alternatives for EP20K1000CF672C9N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EP20K1000CF672C9N Maximum Ratings & Electrical Characteristics
| Family | APEX 20KC |
| Device Type | Loadable PLD / FPGA |
| System Gates | 1,000,000 |
| Logic Elements | 38,400 |
| Embedded Memory | 327,680 bits |
| Maximum User I/O | 508 |
| Core Voltage | 1.8 V |
| Process Technology | 0.15 micron all-layer copper CMOS |
| Maximum Frequency | 250 MHz |
| Propagation Delay (pin-to-pin) | 1.6 ns |
| Package | 672-ball FC-FBGA (flip-chip) |
| Package Body Size | 27 mm x 27 mm |
| Ball Pitch | 1.0 mm |
| Operating Temperature | 0 C to 85 C (Commercial) |
| PLLs | 4 |
| Mounting Type | Surface Mount |
| MultiVolt I/O Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
EP20K1000CF672C9N Pin Configuration
| Pin A1 | I/O — General-purpose user I/O ball (bank dependent) |
| Pin B2 | I/O — General-purpose user I/O ball |
| Pin C3 | VCCINT — 1.8 V core supply |
| Pin D4 | I/O — General-purpose user I/O ball |
| Pin E5 | GND — Common ground |
| Pin F6 | I/O — General-purpose user I/O ball |
| Pin G7 | VCCIO — I/O bank supply voltage (MultiVolt) |
| Pin H8 | I/O — General-purpose user I/O ball |
| Pin J9 | TCK — JTAG test clock |
| Pin K10 | TMS — JTAG test mode select |
| Pin L11 | TDO — JTAG test data out |
| Pin M12 | TDI — JTAG test data in |
| Pin N13 | nSTATUS — Configuration status (open-drain) |
| Pin P14 | nCONFIG — Configuration start (active-low) |
| Pin R15 | CONF_DONE — Configuration complete (open-drain) |
| Pin T16 | DCLK — Configuration clock input |
| Pin U17 | DATA0 — Configuration data input |
| Pin V18 | PLL1_OUTp — PLL1 positive clock output |
| Pin W19 | VCC_PLL1 — PLL1 analog supply |
| Pin Y20 | GND_PLL1 — PLL1 analog ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP20K1000CF672C9N is suitable for 7 applications: Telecommunications Backplane Bridging, ASIC Prototyping, PCI / PCI-X Bus Controller, Industrial Automation Controller, Custom DSP Datapath, Legacy APEX 20KE Replacement / Footprint Reuse, Image Processing Front-End.
Telecommunications Backplane Bridging
The EP20K1000CF672C9N's 1M system gates and 508 user I/O pins make it a strong fit for legacy telecom backplane bridge designs where it aggregates multiple lower-speed TDM/E1 links into a single high-speed fabric. The four on-chip PLLs allow independent clock synthesis for each incoming link domain, while the 327,680 bits of embedded system blocks (ESBs) can buffer small packets on chip without external SRAM. With the 1.6 ns pin-to-pin propagation delay the part can meet tight bus-turn-around budgets typical of legacy HDLC or SDH framers, and the 1.0 mm pitch FC-FBGA keeps the board area reasonable for line-card designs.
Recommended
ASIC Prototyping
With 38,400 logic elements and 1,000,000 system gates, the EP20K1000CF672C9N is large enough to host a substantial ASIC prototype in a single device, partitioning cleanly across LUT logic and embedded memory blocks. The MultiCore architecture lets designers map register-heavy datapaths into LUTs and FIFOs / dual-port RAMs into ESBs in the same die, which preserves timing closure that discrete-FPGA prototypes often lose. The 672-ball FC-FBGA footprint gives plenty of signal pins for bringing out prototype ASIC I/O at full speed, and Quartus II legacy support means existing ASIC regression suites can be re-used unchanged.
Recommended
PCI / PCI-X Bus Controller
The 33 MHz / 66 MHz PCI and 133 MHz PCI-X interfaces require both generous on-chip FIFO memory and careful pin-to-pin skew control - exactly the strengths of the EP20K1000CF672C9N. The 327,680-bit ESB memory fabric can be carved into PCI-X transaction queues and posted-write buffers without external SRAM, while the dedicated MultiVolt I/O banks support the 3.3 V PCI signalling standard directly. The 508 available user I/O pins leave plenty of headroom for 64-bit PCI-X plus a parallel local bus, and the four PLLs can derive the PCI 33/66/133 MHz clocks from a single backplane oscillator.
Recommended
Industrial Automation Controller
Industrial PLC and motion-controller designs benefit from the EP20K1000CF672C9N's mix of on-chip memory for fast deterministic scans and abundant I/O for encoder, resolver, and fieldbus interface glue logic. The four PLLs let the part synthesize independent clocks for Ethernet MAC, Profibus, and high-speed encoder counters in parallel, while the 672-ball FC-FBGA supports the high pin count needed to fan out to many axis-control channels. Commercial 0 to 85 C temperature grade suits cabinet-mounted controllers, and the legacy APEX 20K tool chain keeps long-life industrial designs supportable.
Recommended
Custom DSP Datapath
Custom DSP pipelines such as FIR filters, FFT engines, and video preprocessing benefit from the EP20K1000CF672C9N's 38,400 logic elements combined with 327,680 bits of embedded memory that can be configured as coefficient ROM, delay-line RAM, or dual-port buffer memory. At 250 MHz core speed the part sustains real-time processing of audio and baseband signals, and the LVDS I/O support at up to 508 pins allows direct connection to high-speed ADCs and DACs. Engineers implementing legacy DSP accelerators will find the APEX 20KC's MultiCore architecture a comfortable match for hand-coded datapath RTL.
Recommended
Legacy APEX 20KE Replacement / Footprint Reuse
The EP20K1000CF672C9N is pin-compatible with the earlier APEX 20KE EP20K1000EFC672 series on the same 672-ball FC-FBGA, which makes it the natural upgrade path for designs that need 25 to 35 percent higher fMAX without re-laying out the PCB. Designers migrating legacy Quartus II projects can recompile with the APEX 20KC device library and typically meet timing where the older 20KE failed. This footprint-reuse path is especially valuable for long-life industrial, medical, and military programs that must keep a stable board revision for many years.
Recommended
Image Processing Front-End
Image-processing front-ends for machine vision, medical imaging, and broadcast video benefit from the EP20K1000CF672C9N's combination of wide LVDS I/O (for parallel image-sensor inputs), embedded memory (for line buffers), and 38,400 logic elements (for pipelined pixel processing). The 672-ball FC-FBGA exposes enough pins to bring in 10-bit or 12-bit pixel buses from multiple cameras simultaneously, while the on-chip ESBs reduce the need for external SRAM line buffers. The 250 MHz core speed easily handles 1080p60 video in legacy designs, and the MultiVolt I/O simplifies interfacing to 1.8 V CMOS image sensors.
Recommended
Recommended Products Summary
Engineering reference data for EP20K1000CF672C9N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K1000CF672C8N | EP20K1000CF672C9ES | EP20K1000CF672C7 | EP20K1000CF672C7GZ |
|---|---|---|---|---|---|
| Package | 672-ball FC-FBGA (27x27 mm, 1.0 mm pitch) | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Speed Grade | C9 | C8 (slower) | C9 (engineering sample) | C7 (slowest) | C7 (lead-free) |
| System Gates | 1,000,000 | 1,000,000 | 1,000,000 | 1,000,000 | 1,000,000 |
| Logic Elements | 38,400 | 38,400 | 38,400 | 38,400 | 38,400 |
| Embedded Memory | 327,680 bits | 327,680 bits | 327,680 bits | 327,680 bits | 327,680 bits |
| Maximum User I/O | 508 | 508 | 508 | 508 | 508 |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Operating Temperature | 0 C to 85 C (Commercial) | 0 C to 85 C | 0 C to 85 C (ES) | 0 C to 85 C | 0 C to 85 C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete (ES) | Obsolete | Obsolete |
Key Differentiators
- Highest speed grade (C9) in the APEX 20KC EP20K1000CF672 family (vs EP20K1000CF672C8N)
- 1,000,000 system gates versus 600k of the smaller APEX 20K600 (vs EP20K600CB652C9)
- Pin-compatible upgrade from APEX 20KE (vs EP20K1000EFC672-1)
Design Notes
Estimated: at 250 MHz core frequency with 100 percent toggle rate on a representative 672-ball FC-FBGA design, the EP20K1000CF672C9N draws roughly 1.5 to 2.5 A from the 1.8 V VCCINT rail and a further 0.5 to 1.5 A from VCCIO banks depending on I/O utilization. Follow Altera's PDN decoupling guideline of 0.1 uF X7R plus 10 uF bulk per VCCINT ball group, and place the bulk caps within 100 mil of the balls. Power-rail sequencing must keep VCCINT monotonic with VCCIO within the limits listed in the APEX 20KC datasheet to avoid latch-up on legacy 0.15 micron copper process.
The 27 x 27 mm FC-FBGA package is a flip-chip die with the thermal path through the BGA balls into the PCB. Estimated: without forced airflow and with 2 W total dissipation, junction temperature rises about 18 C above ambient (theta_JA near 9 C/W for a 4-layer JEDEC test board). For 3 W designs in a sealed enclosure, add 200 LFM of airflow or attach a small heat-spreader lid to keep Tj under 100 C. Always validate thermal performance with the APEX 20KC thermal model that Altera provides on request.
Use a 4-layer stack-up with the 1.0 mm-pitch BGA escape routed on the top two layers and continuous power/ground planes on layers 3 and 4. Each BGA escape via should be 8 mil pad / 16 mil drill with micro-via fan-out where the PCB fabricator allows. For LVDS or SSTL interfaces, keep trace lengths matched within 25 mil to meet the APEX 20KC skew budget. Reference the Altera AN 75 'MultiVolt I/O Design Guidelines' for I/O bank placement and VCCIO decoupling patterns.
Do not assume newer Quartus Prime releases support APEX 20KC - the device family was dropped after Quartus II 13.0sp1, so legacy Quartus II must be retained for this part. Avoid mixing the EP20K1000CF672C7, C8, and C9 speed bins in the same timing budget without re-running TimeQuest analysis because the C9 part is the fastest and timing margins differ by speed grade. Finally, ensure that CONF_DONE, nSTATUS, and nCONFIG pull-ups match the datasheet values or configuration will fail at power-up.
Compliance Information
RoHS / REACH / lead-free status not stated explicitly in the verified web data; the 'C9N' suffix on the part number is a legacy Altera designator rather than a guaranteed lead-free marker. Recommend contacting Intel FPGA support or the authorized obsolete distributor for a Material Declaration Sheet before new design-in.
