EP20K1000CF672I9N - 1M Gate APEX 20KC FPGA 672-FBGA | Altera
MPN: EP20K1000CF672I9N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $265 | $2,650.00 |
| 100 | $240 | $24,000.00 |
| 500 | $215 | $107,500.00 |
| 1,000 | $195 | $195,000.00 |
Drop-in alternatives for EP20K1000CF672I9N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EP20K1000CF672I8N
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View Datasheet →EP20K1000CF672C9N
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View Datasheet →EP20K1000CF672I8
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View Datasheet →EP20K1000CF672I9
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View Datasheet →EP20K1000CF672I7
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View Datasheet →EP20K1000CF672I9N Maximum Ratings & Electrical Characteristics
| Family | APEX 20KC |
| Logic Elements / Cells | 38,400 |
| System Gates | 1,000,000 |
| Maximum User I/O | 384 |
| Process Technology | 0.15 µm CMOS |
| Core Voltage | 1.8 V |
| Maximum Internal Frequency | 250 MHz |
| Package | 672-ball FineLine BGA (FC-FBGA) |
| Mounting Type | Surface Mount |
| Embedded Memory | Embedded System Blocks (ESBs) - RAM/ROM/CAM |
| PLLs | Up to 4 |
| Configuration | SRAM-based, volatile |
| Operating Temperature Grade | Industrial (-40C to +100C) |
| Speed Grade | -9 (fastest) |
| JTAG Support | Yes (IEEE 1149.1 boundary scan) |
EP20K1000CF672I9N 672-ball fineline bga (fc-fbga) Pin Configuration Guide
Complete pinout information for EP20K1000CF672I9N (672-ball fineline bga (fc-fbga) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K1000CF672I9N.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP20K1000CF672I9N is suitable for 7 applications: Telecommunications Line Cards, High-Speed Image and Video Processing, ASIC Prototyping and Emulation, Industrial Motor Control and Factory Automation, Military and Aerospace Signal Processing, Test and Measurement Instrumentation, Medical Imaging Systems.
Telecommunications Line Cards
The EP20K1000CF672I9N's 1M system gates and 384 user I/Os make it well-suited for telecom line-card applications where multiple high-speed serial channels and complex framer/MAC functions must coexist on a single programmable device. The LUT-based APEX 20KC fabric runs the datapath logic while embedded system blocks (ESBs) implement FIFO buffers and lookup tables needed for cell/packet processing. At 250 MHz the device comfortably handles OC-48 (2.488 Gbps) pre-processing when distributed across parallel byte lanes. Engineers typically place the FPGA between a network processor and PHY SERDES, using MultiVolt I/O to bridge 3.3 V PHY interfaces with the 1.8 V core. Quartus II place-and-route provides timing-driven synthesis to close multi-cycle paths across the 672-ball BGA.
Recommended
High-Speed Image and Video Processing
With 38,400 logic elements and parallel embedded system blocks, the EP20K1000CF672I9N is engineered for real-time image and video pipelines that require concurrent pixel-domain processing across multiple parallel paths. The 672-ball BGA exposes enough I/O to interface directly to common image sensors (e.g., Camera Link, LVDS-based CCD/CIS interfaces) and HD-SDI video codecs without external bus-multiplexing glue. ESBs configured as dual-port RAM serve as line buffers, while the LUT fabric implements convolution kernels, color-space converters, and motion-estimation engines. Designers working at 1080p60 should expect internal pipeline stages of 150-200 MHz, well within the 250 MHz headroom of the -9 speed grade. Altera's DSP development kit patterns apply directly to this part family.
Recommended
ASIC Prototyping and Emulation
The EP20K1000CF672I9N's 1M-gate capacity, abundant user I/O, and JTAG-based in-system reconfiguration make it a classic ASIC prototyping vehicle for million-gate designs. Multiple devices can be wired together on a prototyping board using their 384 I/Os to model inter-chip ASIC buses. Designers partition their RTL into APEX 20KC-sized blocks, run Quartus II synthesis targeting the -9 speed grade, and iterate rapidly via JTAG bitstream reload — no mask cost, no fab lead time. Embedded system blocks are reused as register files and tag-RAM for cache-coherent prototypes. According to industry ASIC-prototyping guides, FPGAs in this class are still viable for many designs despite the availability of newer families, particularly where cost and tooling familiarity outweigh raw performance.
Recommended
Industrial Motor Control and Factory Automation
The EP20K1000CF672I9N's industrial temperature grade (-40C to +100C) and 384 I/Os suit it for motor-control and factory-automation controllers that must interface to many encoders, resolver feedback channels, and fieldbus ports simultaneously. The 1.8 V core combined with MultiVolt I/O banks at 2.5 V and 3.3 V allows direct connection to industrial RS-485 transceivers, 24 V-isolated digital inputs via optocouplers, and PWM driver stages without external level shifting. ESBs implement S-curve acceleration tables and commutation lookup tables directly on-die. At 250 MHz the FPGA can run field-oriented-control (FOC) loops for multi-axis servo drives within the typical 16-32 kHz control-rate envelope. The 672-ball BGA's fine pitch requires careful PCB thermal design for high-current driver stages in the same enclosure.
Recommended
Military and Aerospace Signal Processing
The EP20K1000CF672I9N industrial-temperature grade and radiation-tolerant circuit techniques make it historically attractive for military and aerospace signal-processing platforms such as radar front-ends, electronic-warfare subsystems, and avionics data buses. The 1M-gate fabric is large enough to implement digital beamforming networks for phased-array antennas, while ESBs hold complex waveform tables. The 672-ball FineLine BGA is hermetically-sealable in many mil-spec board assemblies. For new mil-aero designs, however, designers should evaluate modern rad-hard FPGAs such as Microsemi/Microchip RTG4 or Xilinx Kintex UltraScale; the APEX 20KC is recommended only for legacy refresh programs or as a logic-replacement equivalent on existing qualified boards.
Recommended
Test and Measurement Instrumentation
High-end test and measurement equipment — protocol analyzers, logic-analyzer back-end cards, and arbitrary waveform generators — historically uses APEX 20KC FPGAs like the EP20K1000CF672I9N to parallelize acquisition and pattern-generation tasks across hundreds of channels. The 384 user I/Os allow direct fan-in from multiple test points, while ESBs serve as deep trace buffers and pattern-playback memory. At 250 MHz the FPGA can sustain 8-bit pattern bursts at 200 MHz with sub-nanosecond edge placement. The MultiVolt I/O banks simplify direct interfacing to legacy 5 V test fixtures via 3.3 V-bank operation and external resistive dividers. Quartus II's SignalTap embedded logic analyzer gives designers real-time visibility into internal nodes without external probing — a major productivity win in dense BGA packages.
Recommended
Medical Imaging Systems
The EP20K1000CF672I9N is suitable for medical imaging back-end processing in modalities such as ultrasound beamformers, CT reconstruction pre-processors, and MRI RF-digitizer interfaces. Its 1M-gate fabric runs parallel FIR filter banks and envelope-detection pipelines for ultrasound, while ESBs hold channel-coefficient tables and look-up tables for log-compression. The industrial temperature grade accommodates equipment-room ambient conditions, and the 672-ball BGA's high pin count supports direct interface to multi-channel ADC arrays. At 250 MHz the device can sustain 64-channel parallel beamforming at typical 40 MHz sampling rates. Modern medical designs favor newer low-power FPGA families, but the EP20K1000CF672I9N remains a viable option for cost-sensitive legacy equipment refresh programs.
Recommended
Recommended Products Summary
Engineering reference data for EP20K1000CF672I9N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K1000CF672I8N | EP20K1000CF672C9N | EP20K1000CF672I8 | EP20K1000CF672I9 | EP20K1000CF672I7 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 672-ball FineLine BGA | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same | 672-ball FineLine BGA - same |
| Speed Grade | -9 (fastest) | -8 (~15% slower) | -9 (same) | -8 (~15% slower) | -9 (same) | -7 (~25% slower) |
| Temperature Grade | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Commercial (0C to +85C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) | Industrial (-40C to +100C) |
| System Gates | 1,000,000 | 1,000,000 | 1,000,000 | 1,000,000 | 1,000,000 | 1,000,000 |
| Logic Elements | 38,400 | 38,400 | 38,400 | 38,400 | 38,400 | 38,400 |
| Core Voltage | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Max Internal Frequency | 250 MHz | ~210 MHz (speed grade -8) | 250 MHz | ~210 MHz (speed grade -8) | 250 MHz | ~190 MHz (speed grade -7) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Approx. Single-Piece Price (USD, as of 2026-09-07) | ~$285 | ~$245 (slightly cheaper due to lower speed grade) | ~$265 (commercial temp) | ~$240 | ~$285 (same as -9N) | ~$200 |
Key Differentiators
- Highest speed grade in the APEX 20KC 672-ball BGA family (vs EP20K1000CF672I8N)
- Industrial temperature grade for harsh-environment deployments (vs EP20K1000CF672C9N)
- More headroom than the -7 grade for legacy ASIC prototyping (vs EP20K1000CF672I7)
- Same-family upgrade path with built-in SERDES (vs EP1SGX40DF1020C7N (Stratix GX))
Design Notes
Estimated: at 250 MHz with 50% toggle rate and full I/O switching, the EP20K1000CF672I9N core dissipates roughly 3-6 W. The 672-ball FineLine BGA uses a thermally enhanced die-up substrate but requires PCB copper pours on internal planes and a thermal via array under the central ball grid to keep junction-to-ambient thermal resistance (θJA) within industrial-temperature limits. For high-altitude or sealed enclosures, derate by 20-30% and validate with a thermal probe on the package top.
The 1.8 V VCCINT rail must be sequenced before the MultiVolt VCCIO banks; failing to do so can cause permanent device damage. Place 0.1 µF and 10 µF ceramic decoupling capacitors as close to every power/ground ball pair as possible, using short wide traces on the top layer. According to the APEX 20KC datasheet, bulk 1.8 V regulation should be sized for transient currents of 3-5 A during configuration. A POR (power-on-reset) supervisor with at least 10 ms reset hold is recommended before JTAG configuration begins.
The 672-ball FineLine BGA has a 1.0 mm ball pitch (per APEX 20KC datasheet) which requires laser-drilled microvias and 0.5 oz copper on outer layers for escape routing. Use a 4-6 layer stack-up with dedicated ground and power planes directly beneath the BGA, and stitch the perimeter with grounded vias every 3-5 mm. Reference the Altera APEX 20KC package information datasheet for recommended land-pad and via-keep-out dimensions.
Configuration memory is volatile (SRAM-based) — the device must be re-loaded on every power-up via JTAG, an EPC-series configuration PROM, or a microcontroller. According to Altera's configuration documentation, designers commonly overlook the nCONFIG/nSTATUS/CONF_DONE handshaking, which can leave the device in an undefined state on noisy power rails. Always tie nCONFIG high through a 1-10 kΩ resistor and provide a clean reset edge. Also note that MSEL[2:0] pins must be hard-strapped to the correct configuration mode and cannot be reconfigured at runtime.
Differential clock inputs (CLK[0..n]) should be routed as 100 Ω differential pairs with matched lengths within ±10 mil. According to the APEX 20KC datasheet, PLL feedback loop filter components require a quiet ground island; do not share a ground return with high-current switching I/O. Place PLL components on the same layer as the device within 200 mil of the dedicated PLL pins to minimize loop-filter pickup. LVDS I/O requires 100 Ω termination across the differential pair at the receiver end.
Compliance Information
Compliance data not provided in verified web sources; buyers should request Certificate of Conformity from suppliers for RoHS/REACH/lead-free verification on obsolete-stock purchases.
