EP20K1000CF672C8N - 1M Gate APEX 20KC FPGA, 672-BGA | Intel
MPN: EP20K1000CF672C8N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $252.5 | $2,525.00 |
| 100 | $220.75 | $22,075.00 |
| 500 | $195 | $97,500.00 |
| 1,000 | $178.4 | $178,400.00 |
Drop-in alternatives for EP20K1000CF672C8N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EP20K1000CF672C8N Maximum Ratings & Electrical Characteristics
| Device Family | APEX 20KC |
| Device Type | FPGA (Field Programmable Gate Array) |
| Logic Elements / Cells | 38,400 |
| Equivalent Gate Count | 1,000,000 gates |
| Embedded Memory (bits) | 327,680 |
| Number of I/Os | 488 to 508 |
| Number of Pins / Balls | 672 |
| Package | 672-ball FC-FBGA (Fine-pitch Chip-Scale BGA), 45 x 45 mm, 1.27 mm pitch |
| Mounting Type | Surface Mount |
| Operating Temperature | 0°C to 85°C (Commercial) |
| Supply Voltage (Vccint) | 1.8 V |
| Process Technology | 0.15 µm all-layer copper |
| Internal Operating Frequency (max) | 301.21 MHz |
| Propagation Delay (typ.) | 1.6 ns to 1.79 ns |
| Architecture | MultiCore (LUT + embedded memory + product-term) |
| Pin-to-Pin Compatibility | APEX 20KE family (same 672-ball BGA) |
EP20K1000CF672C8N 672-ball fc-fbga (fine-pitch chip-scale bga), 45 x 45 mm, 1.27 mm pitch Pin Configuration Guide
Complete pinout information for EP20K1000CF672C8N (672-ball fc-fbga (fine-pitch chip-scale bga), 45 x 45 mm, 1.27 mm pitch package) with 672 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP20K1000CF672C8N.
Refer to the datasheet for full pin configuration.
Estimated pin count: 672 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP20K1000CF672C8N is suitable for 6 applications: High-Speed Telecommunications Backplane Bridging, Parallel DSP Coprocessor Engine, PCI / CompactPCI Bus Bridge, Broadcast Video Processing and Routing, ASIC Prototyping and Emulation, Industrial Automation and Motor Control.
High-Speed Telecommunications Backplane Bridging
The EP20K1000CF672C8N's 1M gates, 508 user I/Os, and 327,680 bits of embedded SRAM make it a strong fit for legacy telecom backplane bridging designs where the device aggregates multiple lower-speed TDM or Ethernet streams into a higher-speed uplink. Its 301 MHz internal fabric and 1.6 ns LUT delay support wide parallel datapaths up to 64 bits at 100 MHz, while the embedded memory blocks implement elastic FIFOs without consuming LUT logic. Engineers typically pair the FPGA with external PHY transceivers and use LVTTL or LVCMOS I/O standards at 3.3 V to interface with backplane SERDES devices.
Recommended
Parallel DSP Coprocessor Engine
With 38,400 logic cells and abundant embedded memory, the EP20K1000CF672C8N implements parallel DSP datapaths such as FIR filters, FFT engines, or correlators in legacy signal-processing systems. The device's MultiCore architecture places an Embedded System Block (ESB) inside each MegaLAB, allowing coefficient storage and shift-register implementations to be implemented in dedicated silicon rather than distributed LUT-RAM. Designers targeting >200 MHz pipelined multipliers benefit from the 1.6 ns LUT propagation delay and the 301 MHz maximum internal frequency quoted in the datasheet.
Recommended
PCI / CompactPCI Bus Bridge
The EP20K1000CF672C8N integrates PCI-compliant I/O drivers and supports the 33 MHz/66 MHz PCI standard with up to 508 user I/Os, making it well-suited for legacy PCI-to-local-bus bridges in industrial PCs and CompactPCI systems. The device's 1.8 V core with bank-selectable I/O voltages lets it interface directly to 3.3 V and 5 V PCI slots via on-chip PCI clamping diodes. With 1M gates of logic, the same FPGA can host the bridge controller, a DMA engine, and several peripheral device emulators without external glue logic.
Recommended
Broadcast Video Processing and Routing
Legacy broadcast video routers and frame synchronizers use the EP20K1000CF672C8N for SDI/HD-SDI crosspoint switching, genlocking, and on-screen-display composition. The 508 I/Os accept parallel 10- or 20-bit video buses at 148.5 MHz, while the 327,680 bits of embedded memory buffer line and frame stores without external SRAM in many configurations. The 1.6 ns LUT delay supports real-time pixel-rate processing, and the package's 1.27 mm ball pitch keeps the PCB dense enough for multi-board video routers.
Recommended
ASIC Prototyping and Emulation
Design teams that need to validate large ASIC RTL before tape-out historically used the EP20K1000CF672C8N to host up to 1M gates of synthesized logic in a single device, with multiple FPGAs chained via the abundant I/Os for partitioning. The MultiCore architecture supports a mix of LUT logic, product-term blocks, and embedded memory, which lets designers prototype ASICs that themselves contain microcontrollers, register files, and SRAM blocks. Quartus II provides incremental compilation flows that match this multi-block ASIC emulation methodology.
Recommended
Industrial Automation and Motor Control
The EP20K1000CF672C8N is found in legacy industrial controllers that combine encoder decoding, PWM generation, and EtherCAT-style fieldbus bridging in a single fabric. With 508 I/Os, the FPGA can directly interface to 24 V industrial I/O via external optocouplers and to resolver-to-digital converter front-ends. The 0-85°C commercial temperature range suits most factory-floor enclosures, and the 1.8 V core with 0.15 µm copper process gives acceptable power dissipation for densely populated control boards.
Recommended
Recommended Products Summary
Engineering reference data for EP20K1000CF672C8N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP20K1000CF672C8 | EP20K1000CF672C8ES | EP20K1000CF672C7 | EP20K1000CF672C7ES | EP20K1000CF672C7GZ |
|---|---|---|---|---|---|---|
| Package | 672-ball FC-FBGA (1.27 mm pitch, 45x45 mm) | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Family / Architecture | APEX 20KC / MultiCore | APEX 20KC / MultiCore - same | APEX 20KC / MultiCore - same | APEX 20KC / MultiCore - same | APEX 20KC / MultiCore - same | APEX 20KC / MultiCore - same |
| Speed Grade | C8 (~301 MHz fmax) | C8 (~301 MHz fmax) - same | C8 - same | C7 (~10-15% slower fmax) | C7 | C7 |
| Logic Cells | 38,400 | 38,400 | 38,400 | 38,400 | 38,400 | 38,400 |
| Embedded Memory (bits) | 327,680 | 327,680 | 327,680 | 327,680 | 327,680 | 327,680 |
| Max User I/O | 508 | 508 | 508 | 508 | 508 | 508 |
| Supply Voltage (Vccint) | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V | 1.8 V |
| Operating Temperature | 0°C to 85°C (Commercial) | 0°C to 85°C | 0°C to 85°C (extended screening) | 0°C to 85°C | 0°C to 85°C (extended screening) | 0°C to 85°C |
Key Differentiators
- Highest speed grade in the APEX 20KC 672-ball family (vs EP20K1000CF672C7)
- Tray packaging for prototype / low-volume production (vs EP20K1000CF672C8 (tape-and-reel))
- Pin-compatible with APEX 20KE predecessors (vs APEX 20KE EP20K1000EFC672-x)
Design Notes
The 672-ball FC-FBGA with 1.27 mm pitch requires a 4- or 6-layer PCB with microvia escape routing. Place at least one 0.1 µF X7R decoupling capacitor per VCCIO bank adjacent to the balls, and add four 10 µF tantalum or polymer bulk capacitors near each VCCINT cluster. Use a continuous ground plane on layer 2 directly under the BGA to provide a low-impedance return path for the high-speed I/O switching transients.
Estimated: at 301 MHz with 50% toggle rate across 38,400 logic cells, the APEX 20KC fabric dissipates approximately 1.5-2.5 W typical, 4-5 W worst case. With θJA around 15-20 °C/W for the FC-FBGA on a JEDEC test board, junction temperature rise above ambient is roughly 30-100 °C. Provide a thermal copper pour of at least 4 cm² on the top layer connected to the central BGA ground balls for reliable operation in enclosed industrial enclosures.
Do not confuse the EP20K1000CF672C8N (N suffix = NiPdAu lead-free / NiPd or NiAu BGA ball finish, tray) with the EP20K1000CF672C8ES, which is a supplier-specific extended-screening variant. JTAG configuration pins (TCK, TMS, TDI, TDO, nSTATUS, CONFIG_DONE, nCONFIG) must be pulled correctly per the APEX 20KC datasheet - leaving nCONFIG floating will prevent configuration. Use only Quartus II (or MAX+PLUS II for legacy designs) to generate the .pof / .sof programming file; newer Quartus Prime versions do not support APEX 20KC targets.
Route LVDS pairs (if used) with 100 Ω differential impedance and length-matched to within 150 mil; keep LVDS signals on the top layer over a continuous ground reference. Place the configuration EEPROM (EPC16 or EPC8) within 3 inches of the FPGA and route its parallel or serial interface away from the LVTTL/LVCMOS I/O banks to avoid crosstalk during configuration. Decouple each VCCIO bank independently so mixed-voltage designs (e.g. 3.3 V PCI + 2.5 V processor interface) do not share noisy return paths.
Compliance Information
RoHS, REACH, lead-free, and halogen-free compliance for EP20K1000CF672C8N were not present in the verified web data and are marked [DATA_NEEDED]. AEC-Q100 is not applicable (FPGA is not an automotive-qualified part in this family). Conflict-minerals compliance assumed for Intel/Altera based on standard Intel supplier policy.
