EPM570GT144I5 - MAX II CPLD, 570 LE, 144-TQFP, Industrial | Intel
MPN: EPM570GT144I5 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $29.8 | $2,980.00 |
| 500 | $26.4 | $13,200.00 |
| 1,000 | $23.1 | $23,100.00 |
Drop-in alternatives for EPM570GT144I5 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM570GT144I5N
β Drop-Inβ In Stock
$14.85 / Unit
View Datasheet βEPM570GT144C5N
β Drop-Inβ In Stock
$14.2 / Unit
View Datasheet βEPM570GT144C4N
β Drop-Inβ In Stock
$22.5 / Unit
View Datasheet βEPM570GT144C3N
β Drop-Inβ In Stock
$28.95 / Unit
View Datasheet βEPM570GT144C5
β Drop-Inβ In Stock
$14.2 / Unit
View Datasheet βEPM570GT144I5 Maximum Ratings & Electrical Characteristics
| Family | MAX II |
| Logic Elements (LE) | 570 |
| Macro Cells | 440 |
| User I/Os | 116 |
| Maximum Propagation Delay (tPD) | 5.4 ns |
| Internal Supply Voltage | 1.71 V to 1.89 V |
| Process Technology | 0.18 Β΅m |
| Programmable Type | In System Programmable (Flash) |
| User Flash Memory | 8 Kbits |
| Package | 144-TQFP (20x20 mm) |
| Pin Count | 144 |
| Operating Temperature | -40 Β°C to +100 Β°C (industrial) |
| Mounting Type | Surface Mount |
| Configuration Memory | Non-volatile flash (single-chip) |
| MultiVolt I/O Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| RoHS Status | Compliant |
EPM570GT144I5 Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 8 | GND β Ground |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | I/O β User I/O pin (bank 1) |
| Pin 12 | I/O β User I/O pin (bank 1) |
| Pin 13 | I/O β User I/O pin (bank 1) |
| Pin 14 | I/O β User I/O pin (bank 1) |
| Pin 15 | I/O β User I/O pin (bank 1) |
| Pin 16 | I/O β User I/O pin (bank 1) |
| Pin 17 | I/O β User I/O pin (bank 1) |
| Pin 18 | I/O β User I/O pin (bank 1) |
| Pin 19 | I/O β User I/O pin (bank 1) |
| Pin 20 | I/O β User I/O pin (bank 1) |
| Pin 21 | GND β Ground |
| Pin 22 | VCCINT β Core supply voltage 1.71-1.89 V |
| Pin 23 | I/O β User I/O pin (bank 2) |
| Pin 24 | I/O β User I/O pin (bank 2) |
| Pin 25 | I/O β User I/O pin (bank 2) |
| Pin 26 | I/O β User I/O pin (bank 2) |
| Pin 27 | I/O β User I/O pin (bank 2) |
| Pin 28 | I/O β User I/O pin (bank 2) |
| Pin 29 | I/O β User I/O pin (bank 2) |
| Pin 30 | I/O β User I/O pin (bank 2) |
| Pin 31 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 32 | GND β Ground |
| Pin 33 | I/O β User I/O pin (bank 2) |
| Pin 34 | I/O β User I/O pin (bank 2) |
| Pin 35 | I/O β User I/O pin (bank 2) |
| Pin 36 | I/O β User I/O pin (bank 2) |
| Pin 37 | TDI β JTAG test data input |
| Pin 38 | TMS β JTAG test mode select |
| Pin 39 | TCK β JTAG test clock |
| Pin 40 | GND β Ground |
| Pin 41 | I/O β User I/O pin (bank 2) |
| Pin 42 | I/O β User I/O pin (bank 2) |
| Pin 43 | I/O β User I/O pin (bank 2) |
| Pin 44 | I/O β User I/O pin (bank 2) |
| Pin 45 | I/O β User I/O pin (bank 2) |
| Pin 46 | I/O β User I/O pin (bank 2) |
| Pin 47 | I/O β User I/O pin (bank 2) |
| Pin 48 | I/O β User I/O pin (bank 2) |
| Pin 49 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 50 | GND β Ground |
| Pin 51 | I/O β User I/O pin (bank 2) |
| Pin 52 | I/O β User I/O pin (bank 2) |
| Pin 53 | I/O β User I/O pin (bank 2) |
| Pin 54 | I/O β User I/O pin (bank 2) |
| Pin 55 | I/O β User I/O pin (bank 2) |
| Pin 56 | I/O β User I/O pin (bank 2) |
| Pin 57 | I/O β User I/O pin (bank 2) |
| Pin 58 | I/O β User I/O pin (bank 2) |
| Pin 59 | I/O β User I/O pin (bank 2) |
| Pin 60 | I/O β User I/O pin (bank 2) |
| Pin 61 | GND β Ground |
| Pin 62 | VCCINT β Core supply voltage 1.71-1.89 V |
| Pin 63 | I/O β User I/O pin (bank 3) |
| Pin 64 | I/O β User I/O pin (bank 3) |
| Pin 65 | I/O β User I/O pin (bank 3) |
| Pin 66 | I/O β User I/O pin (bank 3) |
| Pin 67 | I/O β User I/O pin (bank 3) |
| Pin 68 | I/O β User I/O pin (bank 3) |
| Pin 69 | I/O β User I/O pin (bank 3) |
| Pin 70 | I/O β User I/O pin (bank 3) |
| Pin 71 | I/O β User I/O pin (bank 3) |
| Pin 72 | I/O β User I/O pin (bank 3) |
| Pin 73 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 74 | GND β Ground |
| Pin 75 | I/O β User I/O pin (bank 3) |
| Pin 76 | I/O β User I/O pin (bank 3) |
| Pin 77 | I/O β User I/O pin (bank 3) |
| Pin 78 | I/O β User I/O pin (bank 3) |
| Pin 79 | I/O β User I/O pin (bank 3) |
| Pin 80 | I/O β User I/O pin (bank 3) |
| Pin 81 | I/O β User I/O pin (bank 3) |
| Pin 82 | I/O β User I/O pin (bank 3) |
| Pin 83 | I/O β User I/O pin (bank 3) |
| Pin 84 | I/O β User I/O pin (bank 3) |
| Pin 85 | GND β Ground |
| Pin 86 | nCONFIG β Configuration control (active-low) |
| Pin 87 | nSTATUS β Configuration status (active-low) |
| Pin 88 | CONFIG_DONE β Configuration done indicator |
| Pin 89 | DEV_OE β Device-wide output enable (active-low) |
| Pin 90 | DEV_CLRn β Device-wide clear (active-low) |
| Pin 91 | I/O β User I/O pin (bank 3) |
| Pin 92 | I/O β User I/O pin (bank 3) |
| Pin 93 | I/O β User I/O pin (bank 3) |
| Pin 94 | I/O β User I/O pin (bank 3) |
| Pin 95 | I/O β User I/O pin (bank 3) |
| Pin 96 | I/O β User I/O pin (bank 3) |
| Pin 97 | I/O β User I/O pin (bank 3) |
| Pin 98 | I/O β User I/O pin (bank 3) |
| Pin 99 | I/O β User I/O pin (bank 3) |
| Pin 100 | I/O β User I/O pin (bank 3) |
| Pin 101 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 102 | GND β Ground |
| Pin 103 | I/O β User I/O pin (bank 4) |
| Pin 104 | I/O β User I/O pin (bank 4) |
| Pin 105 | I/O β User I/O pin (bank 4) |
| Pin 106 | I/O β User I/O pin (bank 4) |
| Pin 107 | I/O β User I/O pin (bank 4) |
| Pin 108 | I/O β User I/O pin (bank 4) |
| Pin 109 | I/O β User I/O pin (bank 4) |
| Pin 110 | I/O β User I/O pin (bank 4) |
| Pin 111 | GND β Ground |
| Pin 112 | VCCINT β Core supply voltage 1.71-1.89 V |
| Pin 113 | I/O β User I/O pin (bank 4) |
| Pin 114 | I/O β User I/O pin (bank 4) |
| Pin 115 | I/O β User I/O pin (bank 4) |
| Pin 116 | I/O β User I/O pin (bank 4) |
| Pin 117 | I/O β User I/O pin (bank 4) |
| Pin 118 | I/O β User I/O pin (bank 4) |
| Pin 119 | I/O β User I/O pin (bank 4) |
| Pin 120 | I/O β User I/O pin (bank 4) |
| Pin 121 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 122 | GND β Ground |
| Pin 123 | I/O β User I/O pin (bank 4) |
| Pin 124 | I/O β User I/O pin (bank 4) |
| Pin 125 | I/O β User I/O pin (bank 4) |
| Pin 126 | I/O β User I/O pin (bank 4) |
| Pin 127 | I/O β User I/O pin (bank 4) |
| Pin 128 | I/O β User I/O pin (bank 4) |
| Pin 129 | I/O β User I/O pin (bank 4) |
| Pin 130 | I/O β User I/O pin (bank 4) |
| Pin 131 | TDO β JTAG test data output |
| Pin 132 | GND β Ground |
| Pin 133 | I/O β User I/O pin (bank 4) |
| Pin 134 | I/O β User I/O pin (bank 4) |
| Pin 135 | I/O β User I/O pin (bank 4) |
| Pin 136 | I/O β User I/O pin (bank 4) |
| Pin 137 | I/O β User I/O pin (bank 4) |
| Pin 138 | I/O β User I/O pin (bank 4) |
| Pin 139 | I/O β User I/O pin (bank 4) |
| Pin 140 | I/O β User I/O pin (bank 4) |
| Pin 141 | GND β Ground |
| Pin 142 | VCCINT β Core supply voltage 1.71-1.89 V |
| Pin 143 | I/O β User I/O pin (bank 4) |
| Pin 144 | I/O β User I/O pin (bank 4) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570GT144I5 is suitable for 7 applications: Industrial I/O Expansion and Bus Bridging, Power-Sequencer and Reset Controller, LED Display and Matrix Driving, Glue Logic Replacement, Configuration Watchdog for FPGAs, Motor Control Timing and PWM, Test and Measurement Front-End Logic.
Industrial I/O Expansion and Bus Bridging
The EPM570GT144I5 is well suited to industrial I/O expansion and bus bridging between microcontrollers, FPGAs, and peripheral ICs. Its 116 user I/Os and 5.4 ns pin-to-pin delay support fast address decoding for external memory and parallel buses such as 16-bit data plus control signals. The instant-on flash configuration ensures deterministic startup before the main MCU or FPGA is ready, which is critical in factory-automation controllers and PLC I/O modules. MultiVolt I/O banks allow direct interfacing with 1.5 V, 1.8 V, 2.5 V, and 3.3 V logic on the same device.
Recommended
Power-Sequencer and Reset Controller
The EPM570GT144I5 is an excellent fit for power-sequencer and reset-controller ICs in multi-rail systems. The non-volatile flash configuration wakes the device in under 200 Β΅s, allowing it to drive enable signals to DC-DC converters and LDO regulators before the main processor boots. The 570 LEs and 440 macro cells are sufficient for sequencing 6-12 rails with adjustable delays and watchdog logic. The deterministic 5.4 ns timing guarantees that reset pulses meet downstream processor timing requirements without metastability risk.
Recommended
LED Display and Matrix Driving
The EPM570GT144I5 serves as a row/column driver controller in LED display and matrix driving applications. The 116 user I/Os allow direct multiplexing of 8-row by 16-column monochrome panels or 8-row by 8-column RGB panels without external drivers. The MAX II architecture supports PWM generation in firmware, enabling per-LED brightness control at refresh rates above 1 kHz. The industrial temperature range allows operation in outdoor signage and transportation displays, while the in-system programmability simplifies firmware updates in the field.
Recommended
Glue Logic Replacement
The EPM570GT144I5 directly replaces legacy 74HC and 74LVC discrete glue-logic ICs, integrating dozens of AND, OR, NAND, flip-flop, multiplexer, and counter functions into a single package. The 570 LEs typically absorb 15-25 standard 74-series devices, reducing PCB area, BOM cost, and supply-chain complexity. The 144-TQFP package provides enough I/O to handle wide bus decoding and registered buffering, while the flash-based non-volatile configuration eliminates manual jumper setting or socket changes during prototype iterations.
Recommended
Configuration Watchdog for FPGAs
The EPM570GT144I5 is commonly used as a configuration watchdog for larger FPGAs such as Intel Cyclone or Stratix series. The MAX II CPLD boots before the main FPGA is configured, monitors the FPGA's CONFIG_DONE and nSTATUS pins, and triggers a reconfiguration cycle if the FPGA fails to complete startup within a defined window. The 8 Kbits of user flash can store a golden backup bitstream that the CPLD streams to the FPGA on watchdog timeout, providing a robust fault-recovery path in telecommunications and aerospace applications.
Recommended
Motor Control Timing and PWM
The EPM570GT144I5 generates deterministic PWM signals for stepper motor and BLDC motor control applications. With 116 user I/Os, the device can drive up to 8 half-bridges with complementary outputs, hardware dead-time insertion, and fault input handling. The 5.4 ns pin-to-pin delay ensures that commutation events are accurately timed relative to rotor position sensors, reducing torque ripple. The industrial temperature range and 1.8 V core supply suit robotics, CNC machinery, and small electric vehicle controllers where reliability is critical.
Recommended
Test and Measurement Front-End Logic
The EPM570GT144I5 is used in test and measurement instruments as front-end logic for signal routing, channel selection, and trigger conditioning. The 116 user I/Os handle multi-channel analog multiplexer control, range switching relays, and trigger gating at frequencies above 100 MHz when internal counters are cascaded. The instant-on behavior allows the test equipment to enter a known safe state immediately at power-up, protecting sensitive DUTs. The non-volatile configuration stores factory calibration state across power cycles without battery backup.
Recommended
Recommended Products Summary
Engineering reference data for EPM570GT144I5 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570GT144I5N | EPM570GT144C5N | EPM570GT144C4N | EPM570GT144C3N | EPM570GT144C5 |
|---|---|---|---|---|---|---|
| Package | 144-TQFP (20x20) | 144-TQFP (20x20) - same | 144-TQFP (20x20) - same | 144-TQFP (20x20) - same | 144-TQFP (20x20) - same | 144-TQFP (20x20) - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Logic Elements | 570 | 570 | 570 | 570 | 570 | 570 |
| Maximum tPD | 5.4 ns | 5.4 ns | 5.4 ns | 4.0 ns (-26%) | 3.0 ns (-44%) | 5.4 ns |
| Operating Temperature | -40 to +100 C (industrial) | -40 to +100 C (industrial) | 0 to +85 C (commercial) | 0 to +85 C (commercial) | 0 to +85 C (commercial) | 0 to +85 C (commercial) |
| Lead-Free Finish | Yes (Pb-free) | Yes (Pb-free) | Yes (Pb-free) | Yes (Pb-free) | Yes (Pb-free) | No (SnPb) |
| User I/Os | 116 | 116 | 116 | 116 | 116 | 116 |
| Macro Cells | 440 | 440 | 440 | 440 | 440 | 440 |
| Core Voltage | 1.71-1.89 V | 1.71-1.89 V | 1.71-1.89 V | 1.71-1.89 V | 1.71-1.89 V | 1.71-1.89 V |
Key Differentiators
- Industrial temperature grade at the same price as commercial (vs EPM570GT144C5N)
- Faster timing margin available without PCB change (vs EPM570GT144C4N)
- Pb-free finish aligned with modern assembly (vs EPM570GT144C5)
Design Notes
The EPM570GT144I5 requires a separate 1.8 V core rail (VCCINT, 1.71-1.89 V) derived from the system 3.3 V via a low-noise LDO such as the TI TPS7A4533 or equivalent. Each of the four VCCIO banks can be independently supplied at 1.5 V, 1.8 V, 2.5 V, or 3.3 V to support mixed-voltage interfacing. Decoupling: place one 0.1 Β΅F X7R ceramic capacitor within 2 mm of each VCCINT and VCCIO pin, plus a single 10 Β΅F bulk capacitor near the package. Inadequate decoupling causes VCCIO noise that can couple into JTAG signals and produce programming failures.
Estimated: at 30 mA quiescent current and 1.8 V core, the EPM570GT144I5 dissipates approximately 54 mW. The 144-TQFP package has a theta_JA of approximately 26 C/W (with standard JEDEC test board copper), giving a temperature rise of just 1.4 C above ambient - well below the 100 C industrial limit. The exposed-pad variant is not available for the 144-TQFP; rely on internal bond-wire and lead-frame paths. PCB layout should connect all GND pins to a continuous ground plane with at least four vias per GND cluster.
Do not leave JTAG pins (TDI, TMS, TCK, TDO) floating in production - tie TDI and TMS to VCCIO1 through 10 kohm pull-ups and TCK to GND through a 10 kohm pull-down to prevent spurious JTAG state transitions in noisy environments. The nCONFIG pin must be held high in user mode; if pulled low, the device erases and reconfigures, which can cause glitches on the I/O pins. The DEV_OE pin must also be tied high in user mode to enable user I/O outputs; leaving it floating risks high-Z states during power-up.
Long JTAG chains can suffer from signal integrity issues if the TCK frequency exceeds 16 MHz. Keep JTAG trace lengths under 75 mm and avoid routing them parallel to high-frequency switching signals. For multi-device JTAG chains, add a 33 ohm series-termination resistor near the TCK driver to dampen reflections. The Altera MAX II Device Handbook recommends keeping the JTAG signal reference plane (ground) continuous under the JTAG traces, with no splits or voids, to control impedance.
Compliance Information
RoHS compliant per Intel/Altera product page. AEC-Q100 not applicable - this is a CPLD, not an automotive-qualified IC. Halogen-free status not explicitly stated in retrieved web data.
