EPM570GT144C4N - 570 LEs MAX II CPLD, 144-TQFP | Intel
MPN: EPM570GT144C4N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $35.63 | $35.63 |
| 10 | $32.4 | $324.00 |
| 100 | $28.95 | $2,895.00 |
| 500 | $25.1 | $12,550.00 |
| 1,000 | $22.5 | $22,500.00 |
Drop-in alternatives for EPM570GT144C4N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM570GT144C3N
β Drop-Inβ In Stock
$28.95 / Unit
View Datasheet βEPM570GT144I4N
β Drop-Inπ Reference alternative (not in catalog)
EPM570GT144C4
β Drop-Inβ In Stock
$22.1 / Unit
View Datasheet βEPM570GT144C3
β Drop-Inβ In Stock
$13.5 / Unit
View Datasheet βEPM1270GT144C4N
β Drop-Inπ Reference alternative (not in catalog)
EPM240GT144C4N
β Drop-Inπ Reference alternative (not in catalog)
EPM570GT144C4N Maximum Ratings & Electrical Characteristics
| Family | MAX II |
| Logic Elements (LE) | 570 |
| Macrocells | 440 |
| Maximum User I/O | 116 |
| User Flash Memory (UFM) | 8 Kbit |
| Pin-to-Pin Logic Delay (tPD) | 5.4 ns (C4 speed grade) |
| Supply Voltage (VCCINT) | 3.3 V |
| MultiVolt I/O Support | 1.5 V, 1.8 V, 2.5 V, 3.3 V |
| Operating Temperature | 0 Β°C to +85 Β°C (commercial) |
| Process Technology | 0.18 Β΅m, 6-layer-metal flash |
| Package | 144-pin TQFP |
| Mounting Type | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / ByteBlaster |
| Configuration Memory | Non-volatile internal flash |
| RoHS Status | Compliant |
EPM570GT144C4N Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | GND β Ground |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | I/O β User I/O pin (bank 1) |
| Pin 12 | TDI β JTAG Test Data In |
| Pin 13 | TMS β JTAG Test Mode Select |
| Pin 14 | TCK β JTAG Test Clock |
| Pin 15 | GND β Ground |
| Pin 16 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 17 | I/O β User I/O pin (bank 1) |
| Pin 18 | I/O β User I/O pin (bank 1) |
| Pin 19 | I/O β User I/O pin (bank 1) |
| Pin 20 | I/O β User I/O pin (bank 1) |
| Pin 21 | I/O β User I/O pin (bank 1) |
| Pin 22 | I/O β User I/O pin (bank 1) |
| Pin 23 | I/O β User I/O pin (bank 1) |
| Pin 24 | I/O β User I/O pin (bank 1) |
| Pin 25 | I/O β User I/O pin (bank 1) |
| Pin 26 | I/O β User I/O pin (bank 1) |
| Pin 27 | I/O β User I/O pin (bank 1) |
| Pin 28 | I/O β User I/O pin (bank 1) |
| Pin 29 | GND β Ground |
| Pin 30 | VCCINT β Core supply voltage (3.3 V) |
| Pin 31 | I/O β User I/O pin (bank 2) |
| Pin 32 | I/O β User I/O pin (bank 2) |
| Pin 33 | I/O β User I/O pin (bank 2) |
| Pin 34 | I/O β User I/O pin (bank 2) |
| Pin 35 | I/O β User I/O pin (bank 2) |
| Pin 36 | I/O β User I/O pin (bank 2) |
| Pin 37 | GND β Ground |
| Pin 38 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 39 | I/O β User I/O pin (bank 2) |
| Pin 40 | I/O β User I/O pin (bank 2) |
| Pin 41 | I/O β User I/O pin (bank 2) |
| Pin 42 | I/O β User I/O pin (bank 2) |
| Pin 43 | I/O β User I/O pin (bank 2) |
| Pin 44 | I/O β User I/O pin (bank 2) |
| Pin 45 | I/O β User I/O pin (bank 2) |
| Pin 46 | I/O β User I/O pin (bank 2) |
| Pin 47 | GND β Ground |
| Pin 48 | I/O β User I/O pin (bank 2) |
| Pin 49 | I/O β User I/O pin (bank 2) |
| Pin 50 | I/O β User I/O pin (bank 2) |
| Pin 51 | I/O β User I/O pin (bank 2) |
| Pin 52 | I/O β User I/O pin (bank 2) |
| Pin 53 | I/O β User I/O pin (bank 2) |
| Pin 54 | I/O β User I/O pin (bank 2) |
| Pin 55 | I/O β User I/O pin (bank 2) |
| Pin 56 | I/O β User I/O pin (bank 2) |
| Pin 57 | I/O β User I/O pin (bank 2) |
| Pin 58 | GND β Ground |
| Pin 59 | VCCINT β Core supply voltage (3.3 V) |
| Pin 60 | I/O β User I/O pin (bank 3) |
| Pin 61 | I/O β User I/O pin (bank 3) |
| Pin 62 | I/O β User I/O pin (bank 3) |
| Pin 63 | I/O β User I/O pin (bank 3) |
| Pin 64 | I/O β User I/O pin (bank 3) |
| Pin 65 | I/O β User I/O pin (bank 3) |
| Pin 66 | GND β Ground |
| Pin 67 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 68 | I/O β User I/O pin (bank 3) |
| Pin 69 | I/O β User I/O pin (bank 3) |
| Pin 70 | I/O β User I/O pin (bank 3) |
| Pin 71 | I/O β User I/O pin (bank 3) |
| Pin 72 | I/O β User I/O pin (bank 3) |
| Pin 73 | I/O β User I/O pin (bank 3) |
| Pin 74 | I/O β User I/O pin (bank 3) |
| Pin 75 | I/O β User I/O pin (bank 3) |
| Pin 76 | GND β Ground |
| Pin 77 | I/O β User I/O pin (bank 3) |
| Pin 78 | I/O β User I/O pin (bank 3) |
| Pin 79 | I/O β User I/O pin (bank 3) |
| Pin 80 | I/O β User I/O pin (bank 3) |
| Pin 81 | I/O β User I/O pin (bank 3) |
| Pin 82 | I/O β User I/O pin (bank 3) |
| Pin 83 | I/O β User I/O pin (bank 3) |
| Pin 84 | I/O β User I/O pin (bank 3) |
| Pin 85 | I/O β User I/O pin (bank 3) |
| Pin 86 | I/O β User I/O pin (bank 3) |
| Pin 87 | GND β Ground |
| Pin 88 | VCCINT β Core supply voltage (3.3 V) |
| Pin 89 | I/O β User I/O pin (bank 4) |
| Pin 90 | I/O β User I/O pin (bank 4) |
| Pin 91 | I/O β User I/O pin (bank 4) |
| Pin 92 | I/O β User I/O pin (bank 4) |
| Pin 93 | I/O β User I/O pin (bank 4) |
| Pin 94 | I/O β User I/O pin (bank 4) |
| Pin 95 | GND β Ground |
| Pin 96 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 97 | I/O β User I/O pin (bank 4) |
| Pin 98 | I/O β User I/O pin (bank 4) |
| Pin 99 | I/O β User I/O pin (bank 4) |
| Pin 100 | I/O β User I/O pin (bank 4) |
| Pin 101 | I/O β User I/O pin (bank 4) |
| Pin 102 | I/O β User I/O pin (bank 4) |
| Pin 103 | I/O β User I/O pin (bank 4) |
| Pin 104 | I/O β User I/O pin (bank 4) |
| Pin 105 | GND β Ground |
| Pin 106 | I/O β User I/O pin (bank 4) |
| Pin 107 | I/O β User I/O pin (bank 4) |
| Pin 108 | I/O β User I/O pin (bank 4) |
| Pin 109 | I/O β User I/O pin (bank 4) |
| Pin 110 | I/O β User I/O pin (bank 4) |
| Pin 111 | I/O β User I/O pin (bank 4) |
| Pin 112 | I/O β User I/O pin (bank 4) |
| Pin 113 | I/O β User I/O pin (bank 4) |
| Pin 114 | I/O β User I/O pin (bank 4) |
| Pin 115 | I/O β User I/O pin (bank 4) |
| Pin 116 | GND β Ground |
| Pin 117 | VCCINT β Core supply voltage (3.3 V) |
| Pin 118 | I/O β User I/O pin (bank 1) |
| Pin 119 | I/O β User I/O pin (bank 1) |
| Pin 120 | I/O β User I/O pin (bank 1) |
| Pin 121 | I/O β User I/O pin (bank 1) |
| Pin 122 | I/O β User I/O pin (bank 1) |
| Pin 123 | I/O β User I/O pin (bank 1) |
| Pin 124 | GND β Ground |
| Pin 125 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 126 | I/O β User I/O pin (bank 1) |
| Pin 127 | I/O β User I/O pin (bank 1) |
| Pin 128 | I/O β User I/O pin (bank 1) |
| Pin 129 | I/O β User I/O pin (bank 1) |
| Pin 130 | I/O β User I/O pin (bank 1) |
| Pin 131 | I/O β User I/O pin (bank 1) |
| Pin 132 | I/O β User I/O pin (bank 1) |
| Pin 133 | I/O β User I/O pin (bank 1) |
| Pin 134 | GND β Ground |
| Pin 135 | I/O β User I/O pin (bank 1) |
| Pin 136 | I/O β User I/O pin (bank 1) |
| Pin 137 | I/O β User I/O pin (bank 1) |
| Pin 138 | I/O β User I/O pin (bank 1) |
| Pin 139 | I/O β User I/O pin (bank 1) |
| Pin 140 | I/O β User I/O pin (bank 1) |
| Pin 141 | I/O β User I/O pin (bank 1) |
| Pin 142 | I/O β User I/O pin (bank 1) |
| Pin 143 | I/O β User I/O pin (bank 1) |
| Pin 144 | TDO β JTAG Test Data Out |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570GT144C4N is suitable for 6 applications: Industrial I/O Expansion and Bus Bridging, Power-Up/Power-Down Sequencing for ASICs and Processors, LED Display Driving and Multiplexing, Peripheral Glue Logic in Embedded Systems, JTAG Chain and Boundary-Scan Control, State-Machine and Protocol Conversion Engines.
Industrial I/O Expansion and Bus Bridging
The EPM570GT144C4N is widely used in industrial control boards to expand microcontroller or SoC I/O count, implement bus bridges between mismatched interfaces (e.g., parallel to SPI), and perform address decoding. Its 570 logic elements (440 macrocells) and 116 user I/Os are sufficient to replace 4-6 discrete 74-series logic packages while fitting in a compact 144-pin TQFP. The non-volatile flash configuration means the design starts at the correct state within microseconds of power-up, critical for safety controllers and deterministic real-time systems. MultiVolt I/O support (1.5/1.8/2.5/3.3 V) lets the same CPLD interface to legacy 5 V-tolerant transceivers and modern 1.8 V processors without level shifters. Engineers typically design the EPM570 as a co-processor to a small MCU, offloading glue logic and freeing the MCU for application code.
Recommended
Power-Up/Power-Down Sequencing for ASICs and Processors
The EPM570GT144C4N is ideal for managing power rail sequencing in multi-rail systems. Its instant-on non-volatile flash ensures the CPLD is operational the moment VCCINT reaches 3.3 V, well before downstream regulators stabilize. Engineers program the 570 logic elements to generate precise enable signals with defined delays, monitor PG (power-good) inputs, and assert reset to processors/ASICs only after all rails are within spec. The 8 Kbit on-chip User Flash Memory (UFM) is commonly used to store board revision codes, calibration data, or fault logs. The JTAG interface (IEEE 1149.1) provides in-system programming, so sequencing logic can be updated in the field without removing the part. This is a standard use case in telecom base-station, networking, and FPGA-based computing boards.
Recommended
LED Display Driving and Multiplexing
The EPM570GT144C4N's 440 macrocells and 116 user I/Os make it a strong fit for driving large LED matrices, segment displays, or scan-multiplexed panels. Its deterministic 5.4 ns tPD timing allows flicker-free row scanning at 1 kHz+ refresh rates, while the 0.18 Β΅m flash process provides robust output drive suitable for direct LED cathodes (with appropriate current-limiting resistors). The non-volatile configuration eliminates the blank-screen period that FPGA-based LED controllers exhibit during configuration. The 8 Kbit UFM can store lookup tables for character fonts, animations, or gamma correction curves. Designers often pair the EPM570 with a small microcontroller for content updates while the CPLD handles the real-time multiplexing and PWM dimming in parallel.
Recommended
Peripheral Glue Logic in Embedded Systems
The EPM570GT144C4N excels at consolidating scattered 74HC/74LVC logic into a single non-volatile device. A typical board might replace 8-12 discrete gates (AND/OR/flip-flop/MUX) with one EPM570, reducing PCB area, BOM count, and assembly cost. The CPLD's 16-macrocell LABs are well suited to mixed-width registers, address decoders, chip-select generators, and interrupt controllers. Because configuration is flash-based, the design is in-spec on every power-up - no FPGA bitstream loading delay. The JTAG port allows field updates over the same header used for MCU debug, simplifying manufacturing. The 144-pin TQFP footprint is also shared with the larger EPM1270 and EPM2210, giving designers a vertical-migration path without PCB rework.
Recommended
JTAG Chain and Boundary-Scan Control
With built-in JTAG (IEEE 1149.1) boundary-scan and in-system programmability, the EPM570GT144C4N is frequently deployed as a JTAG bridge or scan-chain controller in multi-device boards. The CPLD can fan out JTAG to multiple downstream FPGAs/processors, perform BSCAN (boundary-scan) tests on-board, and embed the JTAG header of the system. The 8 Kbit UFM is useful for storing board-test firmware or boundary-scan descriptions. The MultiVolt I/O (1.5/1.8/2.5/3.3 V) lets one EPM570 work with mixed-voltage JTAG chains. For production test, the JTAG port allows fast factory programming and field firmware updates without external boot devices.
Recommended
State-Machine and Protocol Conversion Engines
The EPM570GT144C4N's 570 logic elements comfortably implement multi-state controllers and protocol converters such as UART-to-SPI, I2C-to-parallel, or custom serial-to-parallel bridges. Its deterministic 5.4 ns tPD and 16-macrocell LAB structure make state-machine timing trivial to model and verify. Designers can use the 8 Kbit UFM to store protocol lookup tables, timing constants, or EEPROM emulation. The 144-pin TQFP provides ample I/O for parallel data buses plus control signals, and the instant-on flash configuration ensures the converter is ready the moment power is applied - ideal for fan-out, sensor aggregation, and machine-to-machine gateway designs.
Recommended
Recommended Products Summary
Engineering reference data for EPM570GT144C4N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570GT144C3N | EPM570GT144I4N | EPM570GT144C4 | EPM570GT144C3 | EPM1270GT144C4N | EPM240GT144C4N |
|---|---|---|---|---|---|---|---|
| Package | 144-pin TQFP | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Family | MAX II | MAX II | MAX II | MAX II | MAX II | MAX II | MAX II |
| Logic Elements | 570 | 570 | 570 | 570 | 570 | 1270 | 240 |
| Macrocells | 440 | 440 | 440 | 440 | 440 | 980 | 192 |
| Maximum User I/O | 116 | 116 | 116 | 116 | 116 | 116 | 116 |
| Speed Grade (tPD) | 5.4 ns (C4) | 4.5 ns (C3, faster) | 5.4 ns (C4, same) | 5.4 ns (C4, same) | 4.5 ns (C3, faster) | 5.4 ns (C4, same) | 5.4 ns (C4, same) |
| Operating Temperature | 0 Β°C to +85 Β°C (commercial) | 0 Β°C to +85 Β°C (commercial) | -40 Β°C to +100 Β°C (industrial) | 0 Β°C to +85 Β°C (commercial) | 0 Β°C to +85 Β°C (commercial) | 0 Β°C to +85 Β°C (commercial) | 0 Β°C to +85 Β°C (commercial) |
Key Differentiators
- Faster speed grade available in same package (vs EPM570GT144C3N)
- Industrial temperature range in same package (vs EPM570GT144I4N)
- Vertical migration within same package (vs EPM1270GT144C4N and EPM240GT144C4N)
Design Notes
The EPM570GT144C4N requires a 3.3 V VCCINT core supply and one or more VCCIO bank supplies (1.5/1.8/2.5/3.3 V) selected per I/O bank. Decouple each VCCINT pin with a 0.1 Β΅F X7R ceramic capacitor placed within 3 mm of the pin, and add a 10 Β΅F bulk capacitor at the regulator output. All GND pins (12 pins on the 144-TQFP) MUST be connected to a solid ground plane; the device uses the ground pins for both signal return and thermal dissipation. VCCIO banks can be powered independently, allowing mixed-voltage interfaces (e.g., 3.3 V to MCU + 1.8 V to DSP) on the same die without external level shifters.
Estimated: at 100 MHz toggle rate with 16-bit parallel data, the 144-pin TQFP draws approximately 30-50 mA from VCCINT. Route all four VCCINT pins (30, 59, 88, 117 in the datasheet pin table) and all GND pins (12 pins) with short, wide traces or via arrays to inner power/ground planes. Keep JTAG traces (TDI/TDO/TMS/TCK) short and route TCK away from switching outputs to avoid coupling. For MultiVolt I/O, place 0.1 Β΅F + 10 Β΅F decoupling on each VCCIO bank pin. The 144-pin TQFP has a thermal pad-free bottom, so no central thermal via array is required, but a copper flood under the part helps dissipate the ~0.5 W typical dissipation.
Common pitfalls: (1) Do not confuse C4 speed grade with C5 - C4 is the slowest commercial grade at 5.4 ns tPD; C3 is faster at 4.5 ns; C5 is the slowest. (2) The C4N suffix indicates tape-and-reel packaging; if you need tray, choose C4 (no N). (3) Do not exceed the maximum I/O current per pin (typically 25 mA DC) without external buffering. (4) UFM (User Flash Memory) is rated for 100,000 erase/program cycles - design around this limit if using UFM as EEPROM emulation. (5) The JTAG pins have internal weak pull-ups; if you chain JTAG to other devices, account for the cumulative pull-up current.
Compliance Information
RoHS compliant and lead-free per Altera/Intel MAX II product page. Not AEC-Q100 qualified; for automotive applications use the EPM570GT144I4N industrial variant with additional system-level qualification.
