EPM570T144I5 - 440 Macrocell CPLD, 5.4ns TQFP-144 | Altera
MPN: EPM570T144I5 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.29 | $38.29 |
| 10 | $34.46 | $344.60 |
| 100 | $30.63 | $3,063.00 |
| 500 | $26.8 | $13,400.00 |
| 1,000 | $22.97 | $22,970.00 |
Drop-in alternatives for EPM570T144I5 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM570T144I5N
✅ Drop-In✓ In Stock
$9.4 / Unit
View Datasheet →EPM570T144C5N
✅ Drop-In✓ In Stock
$9.35 / Unit
View Datasheet →EPM570GT144I5
✅ Drop-In✓ In Stock
$23.1 / Unit
View Datasheet →EPM570T144C5
✅ Drop-In✓ In Stock
$17.3 / Unit
View Datasheet →EPM570T144C4N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$25.1 / Unit
View Datasheet →EPM570T144I5 Maximum Ratings & Electrical Characteristics
| Product Type | CPLD (Complex Programmable Logic Device) |
| Family | MAX II |
| Macrocells (Logic Elements) | 440 |
| User I/O | 116 |
| User Flash Memory (UFM) | 8 Kbits |
| Pin-to-Pin Delay (tPD1) | 5.4 ns |
| Maximum Frequency (fMAX) | 304 MHz |
| Supply Voltage - Core | 1.8 V |
| Supply Voltage - I/O Banks | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Package / Case | TQFP-144 (144-LQFP, 20 x 20 mm) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40 °C to +100 °C (industrial) |
| Process Technology | 0.18 µm flash |
| Programming Interface | JTAG (IEEE 1149.1) |
EPM570T144I5 Pin Configuration
| Pin 1 | I/O — User I/O bank 1 |
| Pin 2 | I/O — User I/O bank 1 |
| Pin 3 | I/O — User I/O bank 1 |
| Pin 4 | I/O — User I/O bank 1 |
| Pin 5 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 6 | GND — Ground |
| Pin 7 | I/O — User I/O bank 2 |
| Pin 8 | I/O — User I/O bank 2 |
| Pin 9 | I/O — User I/O bank 2 |
| Pin 10 | I/O — User I/O bank 2 |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O bank 2 |
| Pin 13 | I/O — User I/O bank 2 |
| Pin 14 | I/O — User I/O bank 2 |
| Pin 15 | I/O — User I/O bank 2 |
| Pin 16 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 17 | I/O — User I/O bank 2 |
| Pin 18 | I/O — User I/O bank 2 |
| Pin 19 | I/O — User I/O bank 2 |
| Pin 20 | I/O — User I/O bank 2 |
| Pin 21 | GND — Ground |
| Pin 22 | I/O — User I/O bank 2 |
| Pin 23 | I/O — User I/O bank 2 |
| Pin 24 | I/O — User I/O bank 2 |
| Pin 25 | I/O — User I/O bank 2 |
| Pin 26 | VCCIO2 — I/O bank 2 supply voltage |
| Pin 27 | I/O — User I/O bank 2 |
| Pin 28 | I/O — User I/O bank 2 |
| Pin 29 | I/O — User I/O bank 2 |
| Pin 30 | I/O — User I/O bank 2 |
| Pin 31 | GND — Ground |
| Pin 32 | I/O — User I/O bank 3 |
| Pin 33 | I/O — User I/O bank 3 |
| Pin 34 | I/O — User I/O bank 3 |
| Pin 35 | I/O — User I/O bank 3 |
| Pin 36 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 37 | I/O — User I/O bank 3 |
| Pin 38 | TDI — JTAG Test Data In |
| Pin 39 | TCK — JTAG Test Clock |
| Pin 40 | TMS — JTAG Test Mode Select |
| Pin 41 | I/O — User I/O bank 3 |
| Pin 42 | GND — Ground |
| Pin 43 | VCCINT — Core supply voltage 1.8 V |
| Pin 44 | I/O — User I/O bank 3 |
| Pin 45 | I/O — User I/O bank 3 |
| Pin 46 | I/O — User I/O bank 3 |
| Pin 47 | I/O — User I/O bank 3 |
| Pin 48 | I/O — User I/O bank 3 |
| Pin 49 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 50 | I/O — User I/O bank 3 |
| Pin 51 | I/O — User I/O bank 3 |
| Pin 52 | I/O — User I/O bank 3 |
| Pin 53 | I/O — User I/O bank 3 |
| Pin 54 | GND — Ground |
| Pin 55 | I/O — User I/O bank 3 |
| Pin 56 | I/O — User I/O bank 3 |
| Pin 57 | I/O — User I/O bank 3 |
| Pin 58 | I/O — User I/O bank 3 |
| Pin 59 | I/O — User I/O bank 3 |
| Pin 60 | VCCIO3 — I/O bank 3 supply voltage |
| Pin 61 | I/O — User I/O bank 3 |
| Pin 62 | I/O — User I/O bank 3 |
| Pin 63 | I/O — User I/O bank 3 |
| Pin 64 | I/O — User I/O bank 3 |
| Pin 65 | GND — Ground |
| Pin 66 | I/O — User I/O bank 3 |
| Pin 67 | I/O — User I/O bank 3 |
| Pin 68 | I/O — User I/O bank 3 |
| Pin 69 | I/O — User I/O bank 3 |
| Pin 70 | I/O — User I/O bank 3 |
| Pin 71 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 72 | I/O — User I/O bank 4 |
| Pin 73 | I/O — User I/O bank 4 |
| Pin 74 | I/O — User I/O bank 4 |
| Pin 75 | I/O — User I/O bank 4 |
| Pin 76 | GND — Ground |
| Pin 77 | I/O — User I/O bank 4 |
| Pin 78 | I/O — User I/O bank 4 |
| Pin 79 | I/O — User I/O bank 4 |
| Pin 80 | I/O — User I/O bank 4 |
| Pin 81 | I/O — User I/O bank 4 |
| Pin 82 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 83 | I/O — User I/O bank 4 |
| Pin 84 | I/O — User I/O bank 4 |
| Pin 85 | I/O — User I/O bank 4 |
| Pin 86 | I/O — User I/O bank 4 |
| Pin 87 | GND — Ground |
| Pin 88 | I/O — User I/O bank 4 |
| Pin 89 | I/O — User I/O bank 4 |
| Pin 90 | I/O — User I/O bank 4 |
| Pin 91 | I/O — User I/O bank 4 |
| Pin 92 | I/O — User I/O bank 4 |
| Pin 93 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 94 | I/O — User I/O bank 4 |
| Pin 95 | I/O — User I/O bank 4 |
| Pin 96 | I/O — User I/O bank 4 |
| Pin 97 | I/O — User I/O bank 4 |
| Pin 98 | GND — Ground |
| Pin 99 | I/O — User I/O bank 4 |
| Pin 100 | I/O — User I/O bank 4 |
| Pin 101 | TDO — JTAG Test Data Out |
| Pin 102 | I/O — User I/O bank 4 |
| Pin 103 | I/O — User I/O bank 4 |
| Pin 104 | I/O — User I/O bank 4 |
| Pin 105 | VCCIO4 — I/O bank 4 supply voltage |
| Pin 106 | I/O — User I/O bank 4 |
| Pin 107 | I/O — User I/O bank 4 |
| Pin 108 | I/O — User I/O bank 4 |
| Pin 109 | I/O — User I/O bank 4 |
| Pin 110 | I/O — User I/O bank 4 |
| Pin 111 | GND — Ground |
| Pin 112 | I/O — User I/O bank 4 |
| Pin 113 | I/O — User I/O bank 4 |
| Pin 114 | I/O — User I/O bank 4 |
| Pin 115 | I/O — User I/O bank 4 |
| Pin 116 | VCCINT — Core supply voltage 1.8 V |
| Pin 117 | I/O — User I/O bank 1 |
| Pin 118 | I/O — User I/O bank 1 |
| Pin 119 | I/O — User I/O bank 1 |
| Pin 120 | GND — Ground |
| Pin 121 | I/O — User I/O bank 1 |
| Pin 122 | I/O — User I/O bank 1 |
| Pin 123 | I/O — User I/O bank 1 |
| Pin 124 | I/O — User I/O bank 1 |
| Pin 125 | I/O — User I/O bank 1 |
| Pin 126 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 127 | I/O — User I/O bank 1 |
| Pin 128 | I/O — User I/O bank 1 |
| Pin 129 | I/O — User I/O bank 1 |
| Pin 130 | I/O — User I/O bank 1 |
| Pin 131 | I/O — User I/O bank 1 |
| Pin 132 | GND — Ground |
| Pin 133 | I/O — User I/O bank 1 |
| Pin 134 | I/O — User I/O bank 1 |
| Pin 135 | I/O — User I/O bank 1 |
| Pin 136 | I/O — User I/O bank 1 |
| Pin 137 | I/O — User I/O bank 1 |
| Pin 138 | VCCIO1 — I/O bank 1 supply voltage |
| Pin 139 | I/O — User I/O bank 1 |
| Pin 140 | I/O — User I/O bank 1 |
| Pin 141 | I/O — User I/O bank 1 |
| Pin 142 | I/O — User I/O bank 1 |
| Pin 143 | I/O — User I/O bank 1 |
| Pin 144 | I/O — User I/O bank 1 |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570T144I5 is suitable for 6 applications: Industrial Control I/O Expansion & Bus Bridging, Telecom Line Card Glue Logic, Power-Up Sequencer for Multi-Rail Systems, ASIC/Discrete-Logic Consolidation, Embedded SBC Address Decoding & Interrupt Routing, Test & Measurement Instrumentation Front-End.
Industrial Control I/O Expansion & Bus Bridging
The EPM570T144I5's 116 user I/O and 440 macrocells make it well suited to industrial control designs that need to bridge between legacy parallel buses (ISA, PC/104, address/data demultiplexed buses) and modern microcontrollers. Its 5.4 ns tPD1 supports glue-logic timing paths up to roughly 185 MHz, sufficient for synchronous address decoding and chip-select generation. Instant-on from non-volatile storage avoids bootloader complications when an MCU has crashed, allowing the CPLD to drive deterministic reset vectors. With the industrial -40 °C to +100 °C temperature range, the part is suitable for factory-floor equipment and outdoor controllers.
Recommended
Telecom Line Card Glue Logic
Telecommunications line cards require deterministic, fast response to interrupt, clock, and reset events. The EPM570T144I5's deterministic timing (no SRAM-config latency), 5.4 ns pin-to-pin delay, and JTAG-driven ISP simplify board bring-up and field firmware updates. The multi-voltage I/O banks (1.5 V to 3.3 V) directly interface legacy 3.3 V line-card ASICs alongside newer 1.8 V DSPs and SERDES chips without external level shifters. Use cases include backplane address decoding, TDM bus multiplexing, and clock distribution gating for ATCA/uTCA platforms.
Recommended
Power-Up Sequencer for Multi-Rail Systems
When system boards require strict power-up and power-down sequencing of multiple rails (e.g., 0.9 V core, 1.5 V DDR, 2.5 V analog, 3.3 V I/O), the EPM570T144I5 provides a deterministic sequencing engine. Its non-volatile flash configuration ensures that on every power cycle the same sequence is enforced within microseconds - critical for ASICs, FPGAs, and processors that require core-before-I/O rails. The 116 I/O are sufficient to drive dozens of enable pins and PG signals. Compared with MCU-based sequencers, the CPLD adds no firmware-update risk and boots in <1 ms.
Recommended
ASIC/Discrete-Logic Consolidation
Designs that historically used dozens of 74-series logic gates, multiplexers, and PAL/GAL devices can consolidate the entire logic block into a single EPM570T144I5, reducing PCB area, BOM cost, and assembly time. With 440 macrocells, the device typically replaces 30-60 discrete SSI/MSI packages. The instant-on flash configuration means no boot PROM is needed, and JTAG ISP allows post-assembly logic changes without reworking the board. The TQFP-144 footprint is well suited to 4-layer designs with standard surface-mount assembly lines.
Recommended
Embedded SBC Address Decoding & Interrupt Routing
Single-board computers (SBCs) and ARM/MIPS-based compute modules often need flexible chip-select and interrupt routing between the host CPU and peripheral chips. The EPM570T144I5's 5.4 ns propagation delay supports decoding at 100 MHz+ host bus speeds, and its 116 I/O easily accommodate 8-16 peripheral chip selects plus 16-32 interrupt/gpio lines. The industrial temperature grade and surface-mount TQFP-144 package are well matched to SBC-style designs with passive cooling. Quartus Prime Lite provides a free development environment.
Recommended
Test & Measurement Instrumentation Front-End
Test and measurement equipment (logic analyzers, protocol exercisers, JTAG/boundary-scan controllers) often needs custom stimulus/response logic tightly coupled to an analog front end. The EPM570T144I5 offers 116 user I/O with 5.4 ns timing to drive pattern generators, mux/demux control signals, and trigger logic. Its instant-on behavior eliminates calibration drift after power cycling, and the JTAG interface allows remote in-system firmware updates in deployed test racks. The industrial temperature range covers most lab and field environments.
Recommended
Recommended Products Summary
Engineering reference data for EPM570T144I5 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570T144I5N | EPM570T144C5N | EPM570GT144I5 | EPM570T144C5 | EPM570T144C4N |
|---|---|---|---|---|---|---|
| Package | TQFP-144 | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 440 | 440 | 440 | 440 | 440 | 440 |
| Pin-to-Pin Delay (tPD1) | 5.4 ns | 5.4 ns | 5.4 ns | 5.4 ns | 5.4 ns | ~7 ns (C4 speed grade) |
| Operating Temperature | -40C to +100C (industrial) | -40C to +100C (industrial) | 0C to +85C (commercial) | -40C to +100C (industrial) | 0C to +85C (commercial) | 0C to +85C (commercial) |
| Lead-Free / RoHS | [DATA_NEEDED] | Yes (N suffix = RoHS) | Yes (N suffix = RoHS) | [DATA_NEEDED] | No (non-N = legacy) | Yes (N suffix = RoHS) |
| User I/O | 116 | 116 | 116 | 116 | 116 | 116 |
| User Flash Memory | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) |
| Approx. Unit Price @ 1000 | $22.97 | ~$23-30 | ~$22-28 | ~$23-30 | ~$18-24 | ~$20-26 |
Key Differentiators
- 440 macrocells - largest MAX II in TQFP-144 (vs EPM240T144 (same TQFP-144 footprint))
- Industrial temperature grade -40C to +100C (vs EPM570T144C5N (commercial 0C to +85C))
- Non-volatile flash configuration with instant-on (vs MAX 10 10M02 (SRAM-based FPGA-like CPLD))
- Multi-voltage I/O banks 1.5V-3.3V without level shifters (vs Discrete 74-series logic)
Design Notes
The EPM570T144I5 requires a clean 1.8 V supply on VCCINT pins (43 and 116) and separate VCCIO supplies for each of the four I/O banks (1.5 V / 1.8 V / 2.5 V / 3.3 V). Place a 0.1 µF X7R ceramic decoupling capacitor within 3 mm of every VCC pin, plus a 10 µF bulk capacitor at the regulator output. The device does not require a specific power-up sequence between VCCINT and VCCIO, but all VCC rails must reach their nominal values within 100 ms to ensure proper configuration from flash. Estimated: at fMAX=304 MHz with all 116 I/O switching, dynamic core current can reach ~80 mA.
The TQFP-144 package has a 0.5 mm pitch and a 20 x 20 mm body, requiring a 4-layer PCB with continuous ground and power planes to meet signal-integrity requirements above 100 MHz. Maintain 50-ohm controlled impedance on critical nets (clock, JTAG) and use 8-mil traces with 8-mil spacing. Place the JTAG header (TCK/TMS/TDO/TDI) on the board edge for in-system programming access. Thermal performance is adequate for typical industrial designs without an explicit heatsink, but a 2 x 2 cm copper pour on the top layer beneath the package is recommended.
Do not leave JTAG pins (TCK, TMS, TDI, TDO) floating - tie TDI and TMS high through 10 kohm pull-ups to VCCIO, and pull TCK low through 10 kohm to GND. Floating JTAG pins can cause ISP failure or unpredictable configuration reload on power-up. Also: the MAX II device configures on every power-up from internal flash, so VCCINT must ramp monotonically; use a supervisor IC if your power tree has soft-start edges. I/O banks must not be left unpowered - unused banks should have their VCCIO tied to a valid rail (1.5 V to 3.3 V) to prevent I/O leakage through floating ESD structures.
Estimated: under worst-case industrial conditions (Tj=100 °C) with all 116 I/O driving 8 mA loads at 50 MHz, total power dissipation is approximately 0.5-0.8 W. The TQFP-144 package has a junction-to-ambient thermal resistance of roughly 35 °C/W on a standard 4-layer JEDEC test board, giving a junction-to-ambient temperature rise of 17-28 °C above ambient. The 'I' industrial temperature grade supports -40 °C to +100 °C junction, sufficient for most sealed enclosure designs. Provide an explicit copper pour or thermal via array beneath the exposed pad area (TQFP-144 has no exposed pad, but top-layer copper flood is recommended).
Compliance Information
RoHS and lead-free status not explicitly stated in verified web data for EPM570T144I5 (non-N suffix). The N-suffix variant EPM570T144I5N is documented as RoHS compliant. AEC-Q100 not applicable - this is a commercial/industrial CPLD, not an automotive-qualified part.
